Data Sheet

ADRF5054

APPLICATIONS INFORMATION

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Rev. 0 | 11 of 13

The ADRF5054 has two power supply pins (VDD and VSS) and two

control pins (V1 and V2). Figure 24 shows the external components

and connections for the supply pins. The VDD and VSS pins are

decoupled with a 100 pF multilayer ceramic capacitor. The device

pinout allows the placement of the decoupling capacitors close to

the device. No other external components are needed for bias and

operation, except DC blocking capacitors on the RF pins when

the RF lines are biased at a voltage different than 0 V. See the

Pin Configuration and Function Descriptions section for additional

information.

Figure 24. Recommended Schematic

RECOMMENDATIONS FOR PCB DESIGN

The RF ports are matched to 50 Ω internally and the pinout is

designed to mate a coplanar waveguide (CPWG) with 50 Ω charac-

teristic impedance on the PCB. Figure 25 shows the referenced

CPWG RF trace design for an RF substrate with 8 mil thick Rogers

RO4003C dielectric material. The RF trace with a 16 mil width and

a 13 mil clearance is recommended for 1.7 mil finished copper

thickness.

Figure 25. Example PCB Stackup

Figure 26 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with

densely filled through vias for optimal RF and thermal performance.

The primary thermal path for the device is the bottom side.

Figure 26. PCB Layout

Figure 27 and Figure 28 show the recommended layout from the

device RFx pins to the 50 Ω CPWG on the referenced stackup.

PCB pads are drawn 1:1 to device pads. The ground pads are

drawn solder mask defined, and the signal pads are drawn as pad

defined. The paste mask is designed to match the device pads

without any aperture reduction. The paste mask is divided into

multiple openings for the paddle.

Figure 27. Recommended RFC, RF1 and RF4 Pin Transition