LTM8024 datasheet(8/26 Pages) AD

8 / 26 page

LTM4709

Rev. 0

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EN1, EN2, EN3 (Pins E3, F1, L1): Device Enable. These

pins enable/disable the output. Pulling the EN pin low dis-

ables the output transistor and auxiliary functions. Drive

the EN pin with a digital logic port, an open-collector NPN

or an open-drain N-channel MOSFET terminated with a

pull-up resistor to BIAS. The pull-up resistor must be

less than 200k to meet the VOH condition of the EN pin. If

unused, connect the EN pin to BIAS.

VO10, VO11, VO12, VO20, VO21, VO22, VO30, VO31, VO32

(Pins E4, E5, E6, K5, K6, K7, K2, K3, K4): Output Voltage

Select. These three-state pins combine to select a nom-

inal output voltage from 0.5V to 4.2V. The input logic

low threshold is less than 300mV referenced to GND and

the logic high threshold is greater than 1.9V. The range

between 0.95V and 1.15V defines the logic Hi-Z state.

See Table 1 in the Applications Information section that

defines the VOUT versus output voltage select pins.

PG1, PG2, PG3 (Pins E7, E2, K1): Power Good. The PG

pins are an open-drain N-channel MOSFET output that is

pulled low if one of the following fault modes is detected.

• VOUT is less than 93% of VOUT(NOMINAL) on the rising

edge of VOUT.

• VOUT is less than 90% of VOUT(NOMINAL) on the falling

edge of VOUT.

• Voltage at BIAS pin is less than its undervoltage

lockout threshold.

• Junction temperature exceeds 168°C typically.

These pins are internally connected to PGR1,2,3 (Pins A3,

F3, L3) with a 100k resistor.

PIN FUNCTIONS

LTM8024 数据表(PDF) 8 Page - Analog Devices