LTM8024 datasheet(12/26 Pages) AD

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LTM4709

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

Bias Undervoltage Lockout

An internal undervoltage lockout (UVLO) comparator

monitors the BIAS1,2,3 pin. If BIAS drops below the UVLO

threshold, all functions shut down, the pass transistors

are off, and output currents fall to zero. The typical BIAS

pin UVLO threshold is 2.21V on the rising edge of BIAS.

The UVLO circuit incorporates about 150mV of hysteresis

on the falling edge of BIAS.

High-Efficiency Linear Regulator: Input-to-Output

Voltage Control (VIOC)

The VIOC1 pin is used to control an upstream switch-

ing converter to maintain a constant voltage across the

LTM4709. This maximizes efficiency while maintaining

high PSRR performance. The VIOC1 pin voltage equals

to (VIN – VOUT) + 800mV, where VIN and VOUT are input

voltage and output voltage of LTM4709. The basic

operation of VIOC is shown in Figure 2. In the case that

the internal reference voltage of the upstream switching

regulator VREFSW ≥ 1V, just tie the VIOC1 pin to the feed-

back pin VFB of the switching regulator. This will regulate

the LTM4709’s input-to-output difference to the switch-

ing regulator’s internal reference voltage VREFSW minus

800mV. When paralleling multiple channels of a single

or multiple LTM4709, just connect the VIOC1 pin to the

upstream switching regulator’s feedback pin to achieve

the VIOC function for all paralleled channels. When the

LTM4709 is used for separate outputs, only channel 1 has

a VIOC function. Channel 2 and Channel 3 do not have a

VIOC function when the module is operating in separate

outputs.

While the VIOC buffer is inside the switching converter’s

feedback loop, given the VIOC buffer’s high bandwidth,

the switching converter’s frequency compensation doesn’t

need to be adjusted. Phase delay through the VIOC buffer

is typically less than 2° for frequencies as high as 100kHz.

Hence, the VIOC buffer will be transparent and just act like

an ideal wire within the switching converter’s bandwidth

(which is usually less than 100kHz).

For example, for a switching converter with less than

100kHz bandwidth and a phase margin of 50°, using the

VIOC buffer, the phase margin will degrade by at most 2°.

The phase margin for the switching converter (using the

VIOC pin) will be at least 48°. Given the VIOC buffer is

inside the switching converter’s feedback loop, the total

capacitance on the VIOC pin is required to be below 20pF.

As shown in Figure 3, the input-to-output differential

voltage is easily programmable to support different applica-

tion needs (PSRR vs power dissipation) using Equation 1.

VIN1 – VOUT1 + 0.8V = VREFSW • R1 + R2

(1)

IMONR1

PGR1

VO11

VIOC1

VO10

PG1

VO12

EN1

BIAS1

VOUTS1

VIN1

GND

VREF1

VOUT1

3.3VBIAS

100 F

4.7 F

4709 F02

22 F

0.8VOUT1

VFB

VIN

IMON1

UPSTREAM

SWITCHING

REGULATOR

VREFSW ≥ 1V

0.8V

–

×1

LTM4709

Figure 2.

Input-to-Output Voltage Control (VIOC) Basic Operation

LTM8024 数据表(PDF) 12 Page - Analog Devices

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