AD8045

Rev. A | Page 23 of 24

EXPOSED PADDLE

The AD8045 features an exposed paddle, which lowers the

thermal resistance by 25% compared to a standard SOIC plastic

package. The exposed paddle of the AD8045 is internally con-

nected to the negative power supply pin. Therefore, when laying

out the board, the exposed paddle must either be connected to

the negative power supply or left floating (electrically isolated).

Soldering the exposed paddle to the negative power supply metal

ensures maximum thermal transfer. Figure 74 and Figure 75 show

the proper layout for connecting the SOIC and LFCSP exposed

paddle to the negative supply.

Figure 74. SOIC Exposed Paddle Layout

The use of thermal vias or “heat pipes” can also be incorporated

into the design of the mounting pad for the exposed paddle.

These additional vias help to lower the overall theta junction to

which the amplifier’s exposed paddle is soldered can greatly

reduce the overall thermal resistance “seen” by the AD8045.

Figure 75. LFCSP Exposed Paddle Layout

For existing designs that want to incorporate the AD8045,

electrically isolating the exposed paddle is another option. If the

exposed paddle is electrically isolated, the thermal dissipation is

primarily through the leads, and the thermal resistance of the

However, a thermally conductive and electrically isolated pad

material may be used. A thermally conductive spacer, such as

the Bergquist Company’s Sil-Pad, is an excellent solution to this

problem. Figure 76 shows a typical implementation using

thermal pad material.

THERMAL CONDUCTIVE INSULATOR

Figure 76. SOIC with Thermal Conductive Pad Material

The thermal pad provides high thermal conductivity but

isolates the exposed paddle from ground or other potential. It is

recommended, when possible, to solder the paddle to the nega-

tive power supply plane or trace for maximum thermal transfer.

Note that soldering the paddle to ground shorts the negative

power supply to ground and can cause irreparable damage to

the AD8045.

DRIVING CAPACITIVE LOADS

In general, high speed amplifiers have a difficult time driving

capacitive loads. This is particularly true in low closed-loop

gains, where the phase margin is the lowest. The difficulty arises

equation

L

O

P

C

R

f

2π

1

=

If this pole occurs too close to the unity gain crossover point,

the phase margin degrades. This is due to the additional phase

loss associated with the pole.

The AD8045 output can drive 18 pF of load capacitance directly,

in a gain of +2 with 30% overshoot, as shown in Figure 37.

Larger capacitance values can be driven but must use a snub-

creates a zero that cancels the pole introduced by the load

50 Ω. The value is typically arrived at empirically and based on

the circuit requirements.