AD9513

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

VS

2

CLK

3

CLKB

4

VS

5

SYNCB

6

VREF

7

S10

8

S9

18 OUT2B

19 OUT2

20 VS

21 VS

22 OUT1B

23 OUT1

24 VS

17 VS

TOP VIEW

(Not to Scale)

AD9513

Figure 5. 32-Lead LFCSP Pin Configuration

1

32

8

9

25

24

16

17

THE EXPOSED PADDLE

IS AN ELECTRICAL AND

THERMAL CONNECTION

EXPOSED PAD

(BOTTOM VIEW)

GND

Figure 6. Exposed Paddle

Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to

function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical

ground.

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 4 ,17 ,20, 21,

24, 26, 29, 30

VS

Power Supply (3.3 V).

2

CLK

Clock Input.

3

CLKB

Complementary Clock Input.

5

SYNCB

Used to Synchronize Outputs.

6

VREF

7 to16, 25

S10 to S1, S0

level should be left NC (no connection).

18

OUT2B

Complementary LVDS/Inverted CMOS Output.

19

OUT2

LVDS/CMOS Output.

22

OUT1B

Complementary LVDS/Inverted CMOS Output. OUT6 includes a delay block.

23

OUT1

LVDS/CMOS Output. OUT6 includes a delay block.

27

OUT0B

Complementary LVDS/Inverted CMOS Output. OUT5 includes a delay block.

28

OUT0

LVDS/CMOS Output. OUT5 includes a delay block.

31

GND

Ground. The exposed paddle on the back of the chip is also GND.

32

RSET

Current Set Resistor to Ground. Nominal value = 4.12 kΩ.