AD9513SLASHPCB datasheet(24/28 Pages) AD

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AD9513

Rev. 0 | Page 24 of 28

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9513 do not supply enough

current to provide a full voltage swing with a low impedance

resistive, far-end termination, as shown in Figure 32. The

far-end termination network should match the PCB trace

impedance and provide the desired switching point. The

reduced signal swing may still meet receiver input requirements

in some applications. This can be useful when driving long

trace lengths on less critical nets.

50Ω

10Ω

OUT1/OUT1B

SELECTED AS CMOS

CMOS

3pF

100Ω

Figure 32. CMOS Output with Far-End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9513 offers LVDS outputs that

are better suited for driving long traces where the inherent noise

immunity of differential signaling provides superior

performance for clocking converters.

SETUP PINS (S0 TO S10)

The setup pins that require a logic level of ⅓ VS (internal self-

bias) should be tied together and bypassed to ground via a

capacitor.

The setup pins that require a logic level of ⅔ VS should be tied

together, along with the VREF pin, and bypassed to ground via

a capacitor.

POWER AND GROUNDING CONSIDERATIONS AND

POWER SUPPLY REJECTION

Many applications seek high speed and performance under less

than ideal operating conditions. In these application circuits, the

implementation and construction of the PCB is as important

as the circuit design. Proper RF techniques must be used for

device selection, placement, and routing, as well as power

supply bypassing and grounding to ensure optimum

performance.

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