AD9513SLASHPCB datasheet(23/28 Pages) AD

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AD9513

Rev. 0 | Page 23 of 28

APPLICATIONS

USING THE AD9513 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed, analog-to-digital converter (ADC) is extremely

sensitive to the quality of the sampling clock provided by the

user. An ADC can be thought of as a sampling mixer; any noise,

distortion, or timing jitter on the clock is combined with the

desired signal at the A/D output. Clock integrity requirements

scale with the analog input frequency and resolution, with

higher analog input frequency applications at ≥14-bit resolution

being the most stringent. The theoretical SNR of an ADC is

limited by the ADC resolution and the jitter on the sampling

clock. Considering an ideal ADC of infinite resolution where

the step size and quantization error can be ignored, the available

SNR can be expressed approximately by

⎥

⎦

⎤

⎢

⎣

⎡

SNR

2π

log

where f is the highest analog frequency being digitized.

tj is the rms jitter on the sampling clock.

Figure 29 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)

100

110

= 100f

200f

400f

1ps

2ps

10ps

SNR = 20log

πfATJ

Figure 29. ENOB and SNR vs. Analog Input Frequency

See Application Note AN-756 and Application Note AN-501 at

www.analog.com.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.)

The AD9513 features LVDS outputs that provide differential

clock outputs, which enable clock solutions that maximize

converter SNR performance. The input requirements of the

ADC (differential or single-ended, logic level, termination)

should be considered when selecting the best clocking/

converter solution.

LVDS CLOCK DISTRIBUTION

The AD9513 provides three clock outputs that are selectable as

either CMOS or LVDS levels. LVDS uses a current mode output

stage. The current is 3.5 mA, which yields 350 mV output swing

across a 100 Ω resistor. The LVDS outputs meet or exceed all

ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs

is shown in Figure 30.

LVDS

100Ω

DIFFERENTIAL (COUPLED)

LVDS

100Ω

Figure 30. LVDS Output Termination

See Application Note AN-586 at www.analog.com for more

information on LVDS.

CMOS CLOCK DISTRIBUTION

The AD9513 provides three outputs that are selectable as either

CMOS or LVDS levels. When selected as CMOS, an output

provides for driving devices requiring CMOS level logic at their

clock inputs.

Whenever single-ended CMOS clocking is used, some of the

following general guidelines should be used.

Point-to-point nets should be designed such that a driver has

one receiver only on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line

matching and/or to reduce current transients at the driver.

The value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are also limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than

3 inches are recommended to preserve signal rise/fall times

and preserve signal integrity.

10Ω

MICROSTRIP

GND

5pF

60.4Ω

1.0 INCH

CMOS

Figure 31. Series Termination of CMOS Output

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