AD9513SLASHPCB datasheet(18/28 Pages) AD

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AD9513

Rev. 0 | Page 18 of 28

Synchronization is initiated by pulling the SYNCB pin low for a

minimum of 5 ns. The input clock does not have to be present

at the time the command is issued. The synchronization occurs

after four input clock cycles.

The synchronization applies to clock outputs

•

that are not turned OFF

•

where the divider is not divide = 1 (divider bypassed)

An output with its divider set to divide = 1 (divider bypassed)

is always synchronized with the input clock, with a propagation

delay.

The SYNCB pin must be pulled up for normal operation. Do

not let the SYNCB pin float.

RSET RESISTOR

The internal bias currents of the AD9513 are set by the

RSET resistor. This resistor should be as close as possible to

the value given as a condition in the Specifications section

(RSET = 4.12 kΩ). This is a standard 1% resistor value and should

be readily obtainable. The bias currents set by this resistor

determine the logic levels and operating conditions of the

internal blocks of the AD9513. The performance figures given

in the Specifications section assume that this resistor value is

used for RSET.

VREF

The VREF pin provides a voltage level of ⅔ VS. This voltage is

one of the four logic levels used by the setup pins (S0 to S10).

These pins set the operation of the AD9513. The VREF pin

provides sufficient drive capability to drive as many of the setup

pins as necessary, up to all on a single part. The VREF pin

should be used for no other purpose.

SETUP CONFIGURATION

The specific operation of the AD9513 is set by the logic levels

applied to the setup pins (S10 to S0). These pins use four-state

logic. The logic levels used are VS and GND, plus ⅓ VS and

⅔ VS. The ⅓ VS level is provided by the internal self-biasing on

each of the setup pins (S10 to S0). This is the level seen by a

setup pin that is left not connected (NC). The ⅔ VS level is

provided by the VREF pin. All setup pins requiring the ⅔VS

level must be tied to the VREF pin.

SETUP PIN

S0 TO S10

60kΩ

30kΩ

Figure 23. Setup Pin (S0 to S10) Equivalent Circuit

The AD9513 operation is determined by the combination of

logic levels present at the setup pins. The setup configurations

for the AD9513 are shown in Table 11 to Table 16. The four

logic levels are referred to as 0, ⅓, ⅔, and 1. These numbers

represent the fraction of the VS voltage that defines the logic

levels. See the setup pin thresholds in Table 6.

The meaning of some of the pin settings is changed by the

settings of other pins. For example, S0 determines whether S3,

and S4 sets OUT2 delay (S0 ≠ 0) or OUT2 phase (S0 = 0).

S2 indicates which outputs are in use, as shown in Table 10. This

allows the same pins (S5 and S6, S7 and S8) to determine the

settings for two different outputs, depending on which outputs

are in use.

Table 10. S2 Indicates Which Outputs Are in Use

Outputs

OUT2 Off

1/3

All Outputs On

2/3

OUT0 Off

OUT1 Off

The fine delay values set by S3 and S4 (when the delay is being

used, S0 ≠ 0) are fractions of the full-scale delay. Note that the

longest setting is 15/16 of full scale. The full-scale delay times

are given in Table 3. To determine the actual delay, take the

fraction corresponding to the fine delay setting and multiply by

the full-scale value set by Table 3 corresponding to the S0 value

and add the LVDS or CMOS propagation delay time (see Table 3).

The full-scale delay times shown in Table 11, and referred to

elsewhere, are nominal time values.

The value at S2 also determines whether S5 and S6 set OUT2

divide (S2 ≠ 0) or OUT1 phase (S2 = 0). In addition, S2

determines whether S7 and S8 set OUT1 divide (S2 ≠ 1) or

OUT2 phase (S2 = 1 and S0 ≠ 0). In addition, the value of S2

determines whether S9 and S10 set OUT0 divide (S2 ≠ 2/3) or

OUT2 divide (S2 = 2/3).

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