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LPC804 数据表(PDF) 28 Page - NXP Semiconductors |
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LPC804 数据表(HTML) 28 Page - NXP Semiconductors |
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28 / 89 page  LPC804 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2023. All rights reserved. Product data sheet Rev. 2.1 — 25 July 2023 28 of 87 NXP Semiconductors LPC804 32-bit Arm Cortex-M0+ microcontroller 9.24 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 9.24.1 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. • Supports CPU PIO or DMA back-to-back transfer. • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle). |
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