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GWIXP425BCT 数据表(PDF) 96 Page - Intel Corporation

部件名 GWIXP425BCT
功能描述  Intel짰 IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PDF  134 Pages
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制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

GWIXP425BCT 数据表(HTML) 96 Page - Intel Corporation

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
March 2005
Datasheet
96
Document Number: 252479, Revision: 005
5.5.2.2
USB Interface
For timing parameters, see the USB 1.1 specification. The IXP42X product line and IXC1100
control plane processors’ USB 1.1 interface is a device or function controller only. The IXP42X
product line and IXC1100 control plane processors’ USB v 1.1 interface cannot be line-powered.
Table 45.
PCI Bus Signal Timings
Symbol
Parameter
33 MHz
66 MHz
Units
Notes
Min.
Max.
Min.
Max.
Tclk2outb
Clock to output for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
2111
6
ns
1, 2, 5,
7, 8
Tclk2out
Clock to output for all point-to-point
signals. This is the PCI_GNT_N
and PCI_REQ_N(0) only.
212
1
6
ns
1, 2, 5,
7, 8
Tsetupb
Input setup time for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
73
ns
4, 6, 7,
8
Tsetup
Input setup time for all point-to-
point signals. This is the
PCI_REQ_N and PCI_GNT_N(0)
only.
10, 12
5
ns
4, 7, 8
Thold
Input hold time from clock.
0
0
ns
4, 7, 8
Trst-off
Reset active-to-output float delay
40
40
ns
5, 6, 7,
8
Notes:
1.
See the timing measurement conditions.
2.
Parts compliant to the 3.3 V signaling environment.
3.
REQ# and GNT# are point-to-point signals and have different output valid delay and input setup
times than do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has
a setup of 12 ns for 33 MHz and 5 ns for 66 MHz.
4.
RST# is asserted and de-asserted asynchronously with respect to CLK.
5.
All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
6.
Setup time applies only when the device is not driving the pin. Devices cannot drive and receive
signals at the same time.
7.
Timing was tested with a 70-pF capacitor to ground.
8.
For additional information, see the PCI Local Bus Specification, Rev. 2.2.



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