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GWIXP425BCT 数据表(PDF) 99 Page - Intel Corporation |
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GWIXP425BCT 数据表(HTML) 99 Page - Intel Corporation |
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99 / 134 page  Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet March 2005 Document Number: 252479, Revision: 005 99 5.5.2.5 MDIO Figure 22. MDIO Output Timings Note: NPE is sourcing MDIO. Figure 23. MDIO Input Timings Note: PHY is sourcing MDIO. Table 50. MDIO Timings Values Symbol Parameter Min. Max. Units Notes T1 ETH_MDIO, clock to output timing with respect to rising edge of ETH_MDC clock ETH_MDC/2 + 10 ns ns T2 ETH_MDIO output hold timing after the rising edge of ETH_MDC clock 10 ns T3 ETH_MDIO input setup prior to rising edge of ETH_MDC clock 2 ns T4 ETH_MDIO hold time after the rising edge of ETH_MDC clock 0 ns 1 T5 ETH_MDC clock period 125 500 ns Note: 1. This parameter is guaranteed by design but has not been 100% tested. A9582-02 ETH_MDC ETH_MDIO T1 T2 A9583-02 ETH_MDC ETH_MDIO T3 T5 T4 |
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