GWIXP425BCT datasheet(119/134 Pages) INTEL

119 / 134 page

Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

119

Table 61.

HPI-16 Multiplexed Read Accesses Values

Symbol

Parameter

Min.

Max.

Units

Notes

Tadd_setup

Valid time that address is asserted on the line. The address

is asserted at the same time as chip select.

Cycles

1, 5, 6

Tcs2hds1val

Delay from chip select being active and the HDS1 data

strobe being active.

Cycles

5, 6

Thds1_pulse

Pulse width of the HDS1 data strobe.

Cycles

2, 4, 5

Tdata_setup

Data is valid from the time from of the falling edge of

HDS1_N to when the data is read.

Cycles

3, 5, 6

Trecov

Time required between successive accesses on the

expansion interface.

217

Cycles

4, 6

Notes:

The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T

clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the

Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to

recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-

active.

The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T

clocks for setup phase.

The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T

clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®

IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to

recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is

de-active.

Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on

the Expansion Bus interface.

HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1

or T3 until HRDY is de-active.

One cycle is the period of the Expansion Bus clock.

Timing tests were performed with a 70-pF capacitor to ground.

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