GWIXP425BCT datasheet(126/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

March 2005

Datasheet

126

Document Number: 252479, Revision: 005

For more information on the HSS Jitter Specifications see the Intel® IXP42X Product Line of

Network Processors and IXC1100 Control Plane Processor Developer’s Manual.

Table 64.

High-Speed, Serial Timing Values

Symbol

Parameter

Min.

Max.

Units

Notes

Setup time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA prior to the rising edge of clock

5ns

1, 2, 3

Hold time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA after the rising edge of clock

0ns

1, 2, 3

Setup time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA prior to the falling edge of clock

5ns

1, 2, 3

Hold time of HSS_TXFRAME, HSS_RXFRAME, and

HSS_RXDATA after the falling edge of clock

0ns

1, 2, 3

Rising edge of clock to output delay for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

1, 4

Falling edge of clock to output delay for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

1, 3, 4

Output Hold Delay after rising edge of final clock for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

0ns

1, 3, 4

Output Hold Delay after falling edge of final clock for

HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA

0ns

1, 3, 4

HSS_TXCLK period and HSS_RXCLK period

1/8.192 MHz 1/512 KHz

Notes:

HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by

the IXP42X product line and IXC1100 control plane processors. The signals are shown to be

synchronous for illustrative purposes and are not required to be synchronous.

Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external

source as inputs into the IXP42X product line and IXC1100 control plane processors. Always

applicable to HSS_RXDATA.

The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling

edge of the given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to

HSS_RXCLK and HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.

Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP42X

product line and IXC1100 control plane processors to an external source. Always applicable to

HSS_TXDATA.

The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP42X

product line and IXC1100 control plane processors. The slowest clock speed that can be accepted or

driven is 512 KHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The clock

duty cycle accepted will be 50/50 + 20%.

Timing tests were performed with a 70-pF capacitor to ground and a 10-K

Ω pull-up resistor.

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