LTC2440IGN datasheet(18/28 Pages) LINER

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LTC2440

sn2440, 2440fas

APPLICATIO S I FOR ATIO

this first rising edge of SCK and concludes after the 32nd

rising edge. Data is shifted out the SDO pin on each falling

edge of SCK. The internally generated serial clock is output

to the SCK pin. This signal may be used to shift the

conversion result into external circuitry. EOC can be

latched on the first rising edge of SCK and the last bit of the

conversion result on the 32nd rising edge of SCK. After the

32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays

HIGH and a new conversion starts.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 9. In order to properly select the OSR

for the conversion following a data abort, five SCK rising

edges must be seen prior to performing a data out abort

(pulling CS HIGH). If CS is pulled high prior to the fifth SCK

falling edge, the OSR selected depends on the number of

SCK signals seen prior to data abort, where subsequent

nonaborted conversion cycles return to the programmed

OSR. On the rising edge of CS, the device aborts the data

output state and immediately initiates a new conversion.

This is useful for systems not requiring all 32-bits of

output data, aborting an invalid conversion cycle, or

synchronizing the start of a conversion.

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. The conversion result is shifted out of the device

by an internally generated serial clock (SCK) signal, see

Figure 10. CS may be permanently tied to ground, simpli-

fying the user interface or isolation barrier. The internal

serial clock mode is selected by tying EXT HIGH.

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the

conversion is complete, SCK, BUSY and SDO go LOW

(EOC = 0) indicating the conversion has finished and the

device has entered the low power sleep state. The part

remains in the sleep state a minimum amount of time

(

≈500ns) then immediately begins outputting data. The

data output cycle begins on the first rising edge of SCK and

Figure 9. Internal Serial Clock, Reduced Data Output Length

SDO

BUSY

SCK

(INTERNAL)

>tEOCtest

MSB

SIG

BIT 8

TEST EOC

BIT 27

BIT 26

BIT 28

BIT 29

BIT 30

EOC

BIT 31

EOC

BIT 0

SLEEP

DATA OUTPUT

Hi-Z

DATA OUTPUT

CONVERSION

SLEEP

2440 F09

<tEOCtest

TEST EOC

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

VCC

REF+

REF–

SCK

BUSY

IN+

IN–

SDO

GND

EXT

1, 8, 9, 16

SDI

VCC

REFERENCE VOLTAGE

0.1V TO VCC

ANALOG INPUT RANGE

–0.5VREF TO 0.5VREF

µF

4.5V TO 5.5V

LTC2440

3-WIRE

SPI INTERFACE

200nV NOISE, 50/60Hz REJECTION

10-SPEED/RESOLUTION PROGRAMMABLE

µV NOISE, 880Hz OUTPUT RATE

VCC

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