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LTC2440IGN 数据表(PDF) 22 Page - Linear Technology

部件名 LTC2440IGN
功能描述  24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution
PDF  28 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC2440IGN 数据表(HTML) 22 Page - Linear Technology

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LTC2440
22
sn2440, 2440fas
SLEEP
CONVERT
SLEEP
CONVERT
SLEEP
8
µA
2440 F15
8mA
8
µA
8mA
8
µA
DATA
OUT
DATA
OUT
CONVERTER
STATE
SUPPLY
CURRENT
CS
Figure 15. Reduced Power Timing Mode
APPLICATIO S I FOR ATIO
LTC2440 Input Structure
Modern delta sigma converters have switched capacitor
front ends that repeatedly sample the input voltage over
some time period. The sampling process produces a small
current pulse at the input and reference terminals as the
capacitors are charged. The LTC2440 switches the input
and reference to a 5pF sample capacitor at a frequency
of 1.8MHz. A simplified equivalent circuit is shown in
Figure 16.
The average input and reference currents can be ex-
pressed in terms of the equivalent input resistance of the
sample capacitor, where:
Req = 1/(fSW • Ceq)
When using the internal oscillator, fSW is 1.8MHz and the
equivalent resistance is approximately 110k
Ω.
Driving the Input and Reference
Because of the small current pulses, excessive lead length
at the analog or reference input may allow reflections or
ringing to occur, affecting the conversion accuracy. The
key to preserving the accuracy of the LTC2440 is complete
settling of these sampling glitches at both the input and
reference terminals. There are several recommended
methods of doing this.
VREF+
VIN+
VCC
RSW (TYP)
500
Ω
ILEAK
ILEAK
VCC
ILEAK
ILEAK
VCC
RSW (TYP)
500
Ω
CEQ
5pF
(TYP)
(CEQ = 3.5pF SAMPLE CAP + PARASITICS)
RSW (TYP)
500
Ω
ILEAK
IIN+
VIN–
IIN–
IREF+
IREF–
2440 F16
ILEAK
VCC
ILEAK
ILEAK
SWITCHING FREQUENCY
fSW = 1.8MHz INTERNAL OSCILLATOR
fSW = fEOSC/5 EXTERNAL OSCILLATOR
VREF–
RSW (TYP)
500
Ω
Figure 16. LTC2440 Input Structure



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