LTC2440

24

sn2440, 2440fas

SCK

BUSY

SDO

CS

EXT

0.1

µF

4

13

5

6

12

1, 8, 9, 16

11

10

15

SDI

7

5V

10

µF

0.01

µF

LTC2440

2440 F19

14

10

Ω

IN+

5k

C2

C2, C5 TAIYO YUDEN JMK107BJ105MA

4.7

µF

8-12V

LT1236-5

1

µF

C1

R1

R2

R4

R5

0.01

µF

C5

1

µF

10

Ω

IN–

5k

C4

0.01

µF

+

–

+

–

fastest expected input signal. Figure 20 shows the large

signal response of the circuit in Figure 19.

3. Measure noise performance of the complete circuit. A

good technique is to build one amplifier for each input,

even if only one will be used in the end application. Bias

both amplifier outputs to midscale, with the inputs tied

together. Verify that the noise is as expected, taking into

account the bandwidth of the LTC2440 inputs for the OSR

being used, the amplifier’s broadband voltage noise and

1/f corner (if any) and any additional noise due to the

amplifier’s current noise and source resistance.

APPLICATIO S I FOR ATIO

For more information on testing high linearity ADCs, refer

to Linear Technology Design Solutions 11.

Input Bandwidth and Frequency Rejection

the digital and analog autocalibration circuits determines

the LTC2440 input bandwidth and rejection characteris-

tics. The digital filter’s response can be adjusted by setting

the oversample ratio (OSR) through the SPI interface or by

Table 6 lists the properties of the LTC2440 with various

Figure 19. Buffering the LTC2440 from High Impedance Sources Using A Chopper Amplifier

Figure 20. Large Signal Input Settling Time Indicates Completed

Settling with Selected Load Capacitance.

2440 F20

100

µs/DIV

Figure 21. Dynamic Input Current is Attenuated by Load

Capacitance and Completly Settled Before the Next Conversion

Sample Resulting in No Reduction in Performance.

2440 F21

5ns/DIV