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LTC2440IGN 数据表(PDF) 19 Page - Linear Technology

部件名 LTC2440IGN
功能描述  24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution
PDF  28 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC2440IGN 数据表(HTML) 19 Page - Linear Technology

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LTC2440
19
sn2440, 2440fas
Figure 10. Internal Serial Clock, Continuous Operation
SDO
BUSY
SCK
(INTERNAL)
CS
LSB24
MSB
SIG
BIT 5
BIT 0
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2410 F10
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
FO
REF+
REF–
SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
4
13
5
6
12
1, 8, 9, 16
11
10
15
SDI
VCC
7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
µF
4.5V TO 5.5V
LTC2440
2-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2
µV NOISE, 880Hz OUTPUT RATE
VCC
APPLICATIO S I FOR ATIO
ends after the 32nd rising edge. Data is shifted out the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2440 significantly
simplifies antialiasing filter requirements.
The LTC2440’s speed/resolution is determined by the over
sample ratio (OSR) of the on-chip digital filter. The OSR
ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz
output rate. The value of OSR and the sample rate fS
determine the filter characteristics of the device. The first
NULL of the digital filter is at fN and multiples of fN where
fN = fS/OSR, see Figure 11 and Table 5. The rejection at the
frequency fN ±14% is better than 80dB, see Figure 12.
If FO is grounded, fS is set by the on-chip oscillator at
1.8MHz
±5% (over supply and temperature variations). At
an OSR of 32,768, the first NULL is at fN = 55Hz and the no
latency output rate is fN/8 = 6.9Hz. At the maximum OSR,
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
180
2440 F11
–80
–100
60
120
240
–120
–140
–20
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)



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