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L6726ATR 数据表(PDF) 17 Page - STMicroelectronics |
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L6726ATR 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 24 page ![]() L6726A Application details 17/24 Type II compensation relies on the zero introduced by the output capacitors bank to achieve stability. Thus, a needed condition to successfully apply type II compensation is (usually true when output capacitor is based on electrolytic, aluminium electrolytic or tantalum capacitor). To define compensation network components values, the below suggestions may be followed: a) Set the output resistor divider in order to obtain the desired output voltage: Usual values of RFB and ROS ranges from some hundreds of Ω to some kΩ (consider trade-off between power dissipation on output resistor divider and offset introduced by FB bias current). If the desired output voltage is equal to internal reference, ROS has to be NC and FB pin can be directly connected to VOUT. b) Set RF in order to obtain the desired closed loop regulator bandwidth according to the approximated formula: If VOUT = VREF, just consider (RFB+ROS)/ROS factor equal to 1. c) Place FZ below FLC (typically 0.2·FLC): d) Place FP at 0.5·FSW: e) Check that compensation network gain is lower than open loop transconductance EA gain. f) Estimate phase margin obtained (it should be greater than 45°) and repeat, modifying parameters, if necessary. 8.3 Soft Start time calculation To calculate SS time (tSS), the following approximated equation can be used (CP<<CF): F ESR F 0dB < R FB R OS ----------- V OUT V REF -------------- 1 – = R F F 0dB F ESR ⋅ F LC 2 ---------------------------------- ∆V OSC V IN ------------------- 1 gm -------- R FB R OS + R OS ---------------------------- ⋅⋅ ⋅ = C F 5 2 π R F F LC ⋅⋅ --------------------------------------- = C P C F π R F C F F SW 1 – ⋅⋅ ⋅ ------------------------------------------------------------ 1 π R F F SW ⋅⋅ ------------------------------------ ≅ = t SS C F V OUT V IN -------------- ∆V OSC ⋅⋅ I SS -------------------------------------------------------- = |
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