MCP3910 datasheet(21/90 Pages) MICROCHIP

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DS20005116D-page 21

MCP3910

3.9

Modulator Outputs

(MDAT0/MDAT1)

MDAT0 and MDAT1 are the output pins for the modulator

serial bitstreams of ADC Channels 0 and 1, respectively.

These pins are high-impedance when the EN_MDAT bit

is logic low. When the EN_MDAT bit is enabled, the

modulator bitstream of each channel is present on the

MDAT0/1 output pins and updated at the AMCLK

frequency (see Section 5.3.5 “Modulator Output

Block”

for a complete description of the modulator out-

puts). These pins can be directly connected to an MCU

or a DSP when a specific digital filtering is needed. When

the MDAT output pins are enabled, the DR output is

disabled. In Two-Wire Interface mode, these pins are

automatically inactive. Their state is high-impedance

during this Two-Wire Interface mode (therefore, these

pins can be left grounded in applications using exclu-

sively this mode; this configuration improves the

EMI/EMC susceptibility of the device).

3.10

Data Ready Output/GAIN1 Logic

Input (DR/GAIN1)

In SPI mode, the Data Ready Output pin indicates if a

new conversion result is ready to be read. The default

state of this pin is logic high when DR_HIZ = 1, and is

high-impedance when DR_HIZ = 0 (default). After each

conversion is finished, a logic low pulse will take place

on the Data Ready pin to indicate the conversion result

is ready as an interrupt. This pulse is synchronous with

the Master Clock and has a defined and constant width.

The Data Ready pin is independent of the SPI interface

and acts like an interrupt output. The Data Ready pin

state is not latched and the pulse width (and period) are

both determined by the MCLK frequency, oversampling

rate, and internal clock prescale settings. The data

ready pulse width is equal to half a DMCLK period and

the frequency of the pulses is equal to DRCLK (see

Figure 1-3).

In Two-Wire Interface mode, this is the GAIN1 logic

select input pin (see Section 7.0 “Two-Wire Serial

Interface Description”

for the logic input table for

GAIN0 and GAIN1). The pin state is latched when the

mode changes to Two-Wire Interface mode and is

relatched at each Watchdog Timer Reset.

3.11

Crystal Oscillator/Master Clock

Input/GAIN0 Logic Input

(OSC1/CLKI/GAIN0)

In SPI mode, OSC1/CLKI and OSC2 provide the Master

Clock for the device. When CLKEXT = 0, a resonant

crystal or clock source with a similar sinusoidal wave-

form must be placed across the OSC1 and OSC2 pins

to ensure proper operation.

The typical clock frequency specified is 4 MHz. For

proper operation, and for optimizing ADC accuracy,

AMCLK should be limited to the maximum frequency

defined in Table 5-2 for the function of the BOOST and

PGA setting chosen. MCLK can take larger values as

long as the prescaler settings (PRE[1:0]) limit

AMCLK = MCLK/PRESCALE in the defined range in

Table 5-2. Appropriate load capacitance should be

connected to these pins for proper operation.

In Two-Wire Interface mode, this is the GAIN0 logic

select input pin (see Section 7.0 “Two-Wire Serial

Interface Description”

for the logic input table for

GAIN0 and GAIN1). The pin state is latched when the

mode changes to Two-Wire Interface mode and is

relatched at each Watchdog Timer Reset.

3.12

Crystal Oscillator Output/

Interface Mode Logic Input

(OSC2/MODE)

When CLKEXT = 0 (default), a resonant crystal or clock

source with a similar sinusoidal waveform must be

placed across the OSC1 and OSC2 pins to ensure

proper operation. Appropriate load capacitance should

be connected to these pins for proper operation.

When CLKEXT = 1 (default condition at POR), this pin

is the Mode Selection pin for the digital interface. When

MODE is logic low, the SPI interface is selected (see

Section 6.0 “SPI Serial Interface Description”

);

when MODE is logic high, the two-wire interface (see

Section 7.0 “Two-Wire Serial Interface Descrip-

tion”

) is selected. The MODE input is latched after a

POR, a Master Reset and/or a Watchdog Timer Reset.

Note:

This pin should not be left floating when the

DR_HIZ bit is low; a 100 k

 pull-up resistor

connected to DVDD is recommended.

Note:

When CLKEXT = 1, the crystal oscillator is

disabled. OSC1 becomes the Master

Clock input, CLKI, a direct path for an

external clock source. One example

would be a clock source generated by an

MCU.

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