MCP3910 datasheet(40/90 Pages) MICROCHIP

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MCP3910

DS20005116D-page 40

 2012-2020 Microchip Technology Inc.

5.8

Hard Reset Effect on Delta-Sigma

Modulator/SINC Filter

In SPI mode, when the RESET pin is logic low, all

ADCs will be in Reset and output code, 0x0000h. The

RESET pin performs a hard Reset (DC biases are still

on, part is ready to convert) and clears all charges con-

tained in the Delta-Sigma modulators. The comparators’

output is ‘0011’ for each ADC.

The SINC filters are all reset, as well as their double-

output buffers. This pin is independent of the serial

interface. It brings all the registers to the default state.

When RESET is logic low, any write with the SPI

interface will be disabled and will have no effect. All

output pins (SDO, DR) are high-impedance.

If MCLK is applied, the input structure is enabled and is

properly biasing the substrate of the input transistors.

In this case, the leakage current on the analog inputs is

low if the analog input voltages are kept between -1V

and +1V.

If MCLK is not applied when in Reset mode, the

leakage can be high if the analog inputs are below

-0.6V, as referred to AGND.

5.9

Phase Delay Block

The MCP3910 incorporates a phase delay generator,

which ensures that CH0 and CH1 ADC are converting

the two analog inputs with a fixed delay between them.

The two ADCs are synchronously sampling, but the

averaging of modulator outputs is delayed so that the

SINC filter outputs (thus the ADC outputs) show a fixed

phase delay, as determined by the PHASE register set-

ting. The odd channel (CH1) is the reference channel

for the phase delay for the CH0/1 pair; it sets the time

reference. Typically, this channel can be the voltage

channel for a single-phase energy metering applica-

tion. The even channel (CH0) is delayed, compared to

the time reference (CH1) by a fixed amount of time

defined in the PHASE register.

The PHASE register contains a 12-bit bank that

represents the delay between the two channels. This

phase value represents the delay of the even channel,

with respect to the associated odd channel, with a

11-bit plus sign, MSB first, two’s complement code.

This code indicates how many DMCLK periods there

are between each channel in the pair (see

Equation 5-5). Since the odd channel is the time

reference, when PHASE[11:0] are positive, the even

channel of the pair is lagging and the odd channel is

leading. When PHASE[11:0] are negative, the even

channel of the pair is leading and the odd channel is

lagging.

EQUATION 5-5:

The timing resolution of the phase delay is 1/DMCLK or

1 µs in the default configuration with MCLK = 4 MHz.

Given the definition of DMCLK, the phase delay is

affected by a change in the prescaler settings

(PRE[1:0]) and the MCLK frequency.

The data ready signals are affected by the phase delay

settings. Typically, the time difference between the data

ready pulses of odd and even channels is equal to the

associated phase delay setting.

Each ADC conversion start, and therefore, each data

ready pulse is delayed by a timing of OSR/2 x DMCLK

periods (equal to half of a DRCLK period). This timing

allows for the odd channel data ready signals to be

located at a fixed time reference (OSR/2 x DMCLK

periods from the Reset), while the even channel can be

leading or lagging around this time reference with the

corresponding PHASE[11:0] delay value.

5.9.1

PHASE DELAY LIMITS

The limits of the phase delays are determined by the

OSR settings: the phase delays can only go from

-OSR/2 to +OSR/2-1 DMCLK periods.

If larger delays between the two channels are needed,

they can be implemented externally to the chip with an

MCU. A FIFO in the MCU can save incoming data from

the leading channel for a number N of DRCLK clocks.

In this case, DRCLK would represent the coarse timing

resolution and DMCLK the fine timing resolution. The

total delay will then be equal to:

EQUATION 5-6:

Note:

For a detailed explanation of the Data

Ready pin behavior, see Figure 5-9.

Note:

Rewriting the PHASE registers with the

same value automatically resets and

restarts all ADCs.

Total Delay =

PHASE[11:0] Decimal Code

DMCLK

Total Delay = N/DRCLK + PHASE/DMCLK

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