MCP3910 datasheet(72/90 Pages) MICROCHIP

72 / 90 page

MCP3910

DS20005116D-page 72

 2012-2020 Microchip Technology Inc.

bit 15

EN_CRCCOM:

CRC-16 Checksum on Serial Communications Enable bit

= CRC-16 checksum is provided at the end of each communication sequence (therefore, each commu-

nication is longer); the CRC-16 message is the complete communication sequence (see Section 6.9

“Securing Read Communications Through CRC-16 Checksum”

for more details)

= Disabled (default)

bit 14

EN_INT:

CRCREG Interrupt Function Enable bit

= The interrupt flag for the CRCREG checksum verification is enabled, the Data Ready pin (DR) will

become logic low and stays logic low if a CRCREG checksum error happens; this interrupt is

cleared if the LOCK[7:0] value is made equal to the PASSWORD value (0xA5)

= The interrupt flag for the CRCREG checksum verification is disabled (default)

bit 13-12

Reserved:

Should be kept equal to ‘0’ at all times

bit 11

EN_MDAT:

Modulator Output Enable bit

= MDAT0/1 outputs are enabled

= MDAT0/1 outputs are disabled and kept in a high-impedance state (default)

bit 10-2

Unimplemented:

Read as ‘0’

bit 1-0

DRSTATUS[1:0]:

Data Ready Status for Each Individual ADC Channel bits

DRSTATUS[n] = 1: Channel CHn data are not ready (default)

DRSTATUS[n] = 0: Channel CHn data are ready, the status bit is set back to ‘1’ after reading the

STATUSCOM register; the status bit is not set back to ‘1’ by the read of the corresponding channel

ADC data

STATUSCOM: STATUS AND COMMUNICATION REGISTER (CONTINUED)

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