MCP3910 datasheet(39/90 Pages) MICROCHIP

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DS20005116D-page 39

MCP3910

5.7

Power-on Reset (POR)

The MCP3910 contains an internal POR circuit that

monitors both analog and digital supply voltages during

operation. The typical threshold for a power-up event

detection is 2.0V, ±5%, and a typical start-up time (tPOR)

of 50 µs. The POR circuit has a built-in hysteresis for

improved transient spike immunity that has a typical

value of 200 mV. Proper decoupling capacitors (0.1 µF

ceramic and 10 µF) should be mounted as close as

possible to the AVDD and DVDD pins, providing

additional transient immunity.

Figure 5-8 illustrates the different conditions at a

power-up and a power-down event under typical

conditions. All internal DC biases are settled at least

1 ms after system POR, under worst-case conditions.

Any data ready pulse occurring within 1 ms, plus the

SINC filter settling time after system Reset, should be

ignored to ensure proper accuracy. After POR, data

ready pulses are present at the pin with all the default

conditions in the Configuration registers.

Both AVDD and DVDD are monitored, so either power

supply can sequence first.

FIGURE 5-8:

Power-on Reset Operation.

Note:

In order to ensure a proper power-up

sequence, the ramp rate of DVDD should

not exceed 3V/µs when coming out of the

POR state.

Additionally, the user should try to lower

the DVDD residual voltage as close to 0V

as possible when the device is kept in a

POR state (below DVDD POR threshold)

for a long time to ensure a proper

power-up sequence. The user can verify if

the

power-up

sequence

has

been

correctly performed by reading the default

state of all the registers in the register map

right after powering up the device. If one

or more of the registers do not show the

proper default settings when being read, a

new power-up cycle should be launched

to recover from this condition.

POR

State

Power-up

Normal

POR

State

Biases are

unsettled.

Conversions

started here may

not be accurate.

Biases are settled.

Conversions started

here are accurate.

Analog Biases

Settling Time

SINC Filter

Settling

Time

Voltage

(AVDD, DVDD)

Time

POR Threshold Up

(2.0V typical)

(1.8V typical)

tPOR

Operation

Any data read pulse

occurring during this time

can yield inaccurate output

data. It is recommended to

discard them.

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