PC7447AMGH1000LB datasheet(7/44 Pages) ATMEL

7 / 44 page

5387B–HIREL–07/05

PC7447A [Preliminary]

– Store merging for multiple store misses to the same line. Only coherency action

taken (address-only) for store misses merged to all 32 bytes of a cache block (no

data tenure needed)

– Three-entry finished store queue and five-entry completed store queue between the

LSU and the L1 data cache

– Separate additional queues for efficient buffering of outbound data (such as castouts

and write-through stores) from the L1 data cache and L2 cache

• Multiprocessing support features include the following:

– Hardware-enforced, MESI cache coherency protocols for data cache

– Load/store with reservation instruction pair for atomic memory references,

semaphores, and other multiprocessor operations

• Power and thermal management

– A new dynamic frequency switching (DFS) feature allows the processor core

frequency to be halved through software to reduce power consumption

– The following three power-saving modes are available to the system:

Nap: Instruction fetching is halted. Only the clocks for the time base, decrementer,

and JTAG logic remain running. The part goes into the doze state to snoop memory

operations on the bus and then back to nap using a QREQ/QACK processor-system

handshake protocol.

Sleep: Power consumption is further reduced by disabling bus snooping, leaving

only the PLL in a locked and running state. All internal functional units are disabled.

Deep sleep: When the part is in the deep Sleep state, the system can disable the

PLL. The system can then disable the SYSCLK source for greater system power

savings. Power-on reset procedures for restarting and relocking the PLL must be

followed upon exiting the deep sleep state.

– Instruction cache throttling provides control of instruction fetching to limit device

temperature

– A new temperature diode that can determine the temperature of the microprocessor

• Performance monitor can be used to help debug system designs and improve software

efficiency

• In-system testability and debugging features through JTAG boundary-scan capability

• Testability

– LSSD scan design

– IEEE 1149.1 JTAG interface

– Array built-in self test (ABIST), factory test only

• Reliability and serviceability

– Parity checking on system bus

– Parity checking on the L1 and L2 caches

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