PC7447AMGH1000LB datasheet(6/44 Pages) ATMEL

6 / 44 page

5387B–HIREL–07/05

PC7447A [Preliminary]

– Instruction cache can provide four instructions per clock cycle; data cache can

provide four words per clock cycle

– Caches can be disabled in software

– Caches can be locked in software

– MESI data cache coherency maintained in hardware

– Separate copy of data cache tags for efficient snooping

– Parity support on cache and tags

– No snooping of instruction cache except for icbi instruction

– Data cache supports AltiVec LRU and transient instructions

– Critical double- and/or quad-word forwarding is performed as needed. Critical quad-

word forwarding is used for AltiVec loads and instruction fetches. Other accesses

use critical double-word forwarding.

• Level 2 (L2) cache interface

– On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache

– Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

– A total nine-cycle load latency for an L1 data cache miss that hits in L2

– Cache write-back or write-through operation programmable on a per-page or per-

block basis 64-byte, two-sectored line size

– Parity support on cache

• Separate memory management units (MMUs) for instructions and data

– 52-bit virtual address, 32- or 36-bit physical address

– Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte

segments

– Memory programmable as write-back/write-through, caching-inhibited/caching-

allowed, and memory coherency enforced/memory coherency not enforced on a

page or block basis

– Separate IBATs and DBATs (eight each) also defined as SPRs

– Separate instruction and data translation look aside buffers (TLBs)

Both TLBs are 128-entry, two-way set-associative, and use a LRU replacement

algorithm

TLBs are hardware- or software-reloadable (that is, a page table search is

performed in hardware or by system software on a TLB miss).

• Efficient data flow

– Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256

bits

– The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs

– L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1

cache

– As many as eight outstanding, out-of-order, cache misses are allowed between the

L1 data cache and the L2 bus

– As many as 16 out-of-order transactions can be present on the MPX bus

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