Soft Shutdown

To avoid excessive dV/dt on the SiC FET or IGBT during fault shut down, the Si828x implements a soft shut down feature to discharge

the switch's gate slowly.

Fault (FLTb) Pin

FLTb is an open-drain type output. A pull-up resistor takes the pin high. When the desaturation condition is detected, the Si828x

indicates the fault by bringing the FLTb pin low. FLTb stays low until the controller resets the desaturation fault by driving the RSTb pin

low.

Note: This FLTb behavior is only valid when, prior to the desaturation condition being detected, there were no undervoltage lockout

(UVLO) conditions.

Reset (RSTb) Pin

The RSTb pin is active low and is used to clear the desaturation condition and bring the Si828x driver back to an operational state.

Even though IN+ and IN- may be toggling, the driver output will not change state until the fault condition has been reset. Both RSTb

and FLTb should be high before resuming operation.

Undervoltage Lockout (UVLO)

The UVLO circuit unconditionally drives VL low when VDDB is below the lockout threshold. The Si828x is maintained in UVLO until

VDDB rises above VDDBUV+. During power down, the Si828x enters UVLO when VDDB falls below the UVLO threshold minus

hysteresis (i.e., VDDB < VDDBUV+ – VDDBHYS).

Note: UVLO voltage is evaluated between VDDB and VMID. The VSSB pin should be shorted to VMID if a negative gate bias is not

utilized.

Ready (RDY) Pin (Si8285 Only)

The ready pin indicates to the controller that power is available on both sides of the isolation, i.e., at VDDA and VDDB. RDY goes high

when both the primary side and secondary side UVLO circuits are disengaged. If the UVLO conditions are detected on either side of

the isolation barrier, the ready pin will return low. RDY is a push-pull output pin and can be floated if not used. The recommendation

is to put a 10kΩ pulldown to ground on this pin to help prevent a false "Ready" indication when power supplies are below operating

conditions (VDDA UVLO active).

Miller Clamp (Si8285 Only)

SiC FET or IGBT power circuits are commonly connected in a half bridge configuration with the collector of the bottom IGBT tied to the

emitter of the top IGBT, or, in the case of SiC FETs, to the drain and source, respectively.

As an example using IGBTs, when the upper switch turns on (while the bottom switch is in the off state), the voltage on the collector of

the bottom switch flies up several hundred volts quickly (fast dV/dt). This fast dV/dt induces a current across the IGBT collector-to-gate

capacitance (CCG) that constitutes a positive gate voltage spike and can turn on the bottom IGBT. This behavior is called Miller parasitic

turn on and can be destructive to the switch since it causes shoot-through current from the positive power rail across the two switches

to ground. The Si828x Miller clamp’s purpose is to clamp the gate of the switch device being driven by the Si828x to prevent switch turn

on due to the collector CCG coupling. SiC FET half bridge behavior is similar and the Miller clamp's purpose similar, with the effect due

to the SiC FET's drain-to-gate capacitance (CDG).

Si8285/86 Data Sheet • Product Overview

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

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Rev. 2.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 12, 2021

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