3.1.3 Reset, RDY, and Fault

The Si8285 has an active high ready (RDY) push-pull output and needs a 10 kΩ pulldown resistor to prevent false ready indications

during power up. On both the Si8285 and Si8286, the open drain fault (FLTb) output needs a pullup resistor (1 kΩ recommended) to

prevent false fault indication in noisy environments; furthermore, the active low reset input (RSTb) needs a 10 kΩ pullup to help avoid

false resets, particularly at startup.. Fast common-mode transients in high-power circuits can inject noise and glitches into these pins

due to parasitic coupling. Depending on the SiC FET or IGBT power circuit layout, additional capacitance (100 pF to 470 pF) can be

included on these pins to prevent false RDY and FLTb indications as well as to prevent unintended RSTb reset of the device.

The FLTb outputs from multiple Si828x devices can be connected in an OR wiring configuration to provide a single FLTb signal to the

MCU.

The Si828x gate driver will shut down when a fault is detected. It then provides FLTb indication to the MCU and remains in the

shutdown state until the MCU applies a reset signal to RSTb.

3.1.4 Desaturation

The Si828x provides sufficient voltage and current to drive and keep the IGBT or SiC FET in saturation during on time to minimize

power dissipation and maintain high-efficiency operation. However, abnormal load conditions can force the switch out of saturation and

cause permanent damage.

The figure below illustrates the Si828x desaturation circuit. When the Si828x driver output is high, the internal current source is on, and

this current flows from the DSAT pin to charge the CBL capacitor. The voltage on the DSAT pin is monitored by an internal comparator.

Since the DSAT pin is connected to the SiC FET drain or IGBT collector through the DDSAT and a small RDSAT, its voltage is almost the

same as the VCE of the IGBT or VDS of the SiC FET. If this VCE or VDS voltage does not drop below the Si828x desaturation threshold

voltage within a certain time after turning on the SiC FET or IGBT (blanking period) the block will generate a fault signal. The Si828x

desaturation hysteresis is fixed at 220 mV and threshold is nominally 7 V.

VMID

DSAT

DESAT Sense

Driver ControlSignal

Fault Signal

Driver Disable

CBL

RDSAT

DDSAT

7 V

Ichg

Figure 3.5. Desaturation Circuit (IGBT Example Shown)

As an additional feature, the Si828x supports a blanking timer function to mask the turn-on transient of the external switching device

and avoid unexpected fault signal generation. This function requires an external blanking capacitor, CBL, between DSAT and VMID

pins. The Si828x includes a current source (IChg) to charge the CBL. This current source, the value of the external CBL, and the

programmed fault threshold, determine the blanking time (tBlanking).

tBlanking = CBI ×

VDESAT

Ichg

An internal NMOS switch is implemented between DSAT and VMID to discharge the external blanking capacitor, CBL, and reset the

blanking timer. The current limiting RDSAT resistor protects the DSAT pin from large current flow toward the SiC FET drain or IGBT

collector during the switch's body diode freewheeling period (in some systems it is possible that the IGBT collector voltage drops below

VMID, causing current to flow in DSAT).

Si8285/86 Data Sheet • Applications Information

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

9

Rev. 2.0 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 12, 2021

9