USB2502-HT datasheet(27/44 Pages) SMSC

27 / 44 page

2-Port USB 2.0 Hub Controller

Datasheet

SMSC USB2502

Revision 2.1 (12-06-06)

DATASHEET

5.3.9.1

5.3.9.2

0Ch

R/W

Max Power (Self)

MAXPS

0Dh

R/W

Max Power (Bus)

MAXPB

0Eh

R/W

Hub Controller

Max Current (Self)

HCMCS

0Fh

R/W

Hub Controller

Max Current (bus)

HCMCB

10h

R/W

Power-on Time

PWRT

BIT

NUMBER

BIT NAME

DESCRIPTION

7:3

Reserved

Reserved. {Note: Software must never write a ‘1’ to these bits}

RESET

Reset the SMBus Interface and internal memory back to RESET_N assertion

default settings. {Note: During this reset, this bit is automatically cleared to

its default value of 0.}

0 = Normal Run/Idle State.

1 = Force a reset.

WRITE_PROT

Write Protect: The external SMBus host sets this bit after the Hub’s internal

memory is loaded with configuration data. {Note: The External SMBus Host

is responsible for verification of downloaded data.}

0 = The internal memory (address range 01-10h) is not write protected.

1 = The internal memory (address range 01-10h) is “write-protected” to

prevent unintentional data corruption.}

{Note: This bit is write once and is only cleared by assertion of the external

RESET_N pin.}

USB_ATTACH

USB Attach & power-down the SMBus Interface.

0 = Default; SMBus slave interface is active.

1 = Hub will signal a USB attach event to an upstream device, Note: SMBus

Slave interface will completely power down after the ACK has completed.

{Note: This bit is write once and is only cleared by assertion of the external

RESET_N pin.}

BIT

NUMBER

BIT NAME

DESCRIPTION

7:0

VID_LSB

Least Significant Byte of the Vendor ID.

Table 5.4 SMBus Slave Interface Register Map (continued)

REG

ADDR

R/W

ABBR

BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

USB2502-HT 数据表(PDF) 27 Page - SMSC Corporation

USB2502-HT 数据表(HTML) 27 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载