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MPC5200 数据表(PDF) 21 Page - Freescale Semiconductor, Inc |
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MPC5200 数据表(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 80 page  Electrical and Thermal Characteristics MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor 21 Figure 6. Timing Diagram—Standard SDRAM Memory Write Timing 3.3.5.3 Memory Interface Timing-DDR SDRAM Read Command The SDRAM Memory Controller uses an internally skewed clock for reading DDR memory. The programmable bits in the Reset Configuration Register used to account for unknown board delays are in the CDM module. The internal read clock can be delayed up to 3 ns under worst operating conditions in 32 increments of 95 ps, (1.4 ns in 45 ps increments under best case operating conditions) by programming the CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration register are not ‘reset configured’ but have a hard coded reset value and are writable during operation. Table 19. Standard SDRAM Write Timing Sym Description Min Max Units SpecID tmem_clk MEM_CLK period 7.5 — ns A5.8 tvalid Control Signals, Address and MBA Valid after rising edge of MEM_CLK —tmem_clk*0.5+0.4 ns A5.9 thold Control Signals, Address and MBA Hold after rising edge of MEM_CLK tmem_clk*0.5 — ns A5.10 DMvalid DQM valid after rising edge of MEM_CLK — tmem_clk*0.25+0.4 ns A5.11 DMhold DQM hold after rising edge of Mem_clk tmem_clk*0.25-0.7 — ns A5.12 datavalid MDQ valid after rising edge of MEM_CLK — tmem_clk*0.75+0.4 ns A5.13 datahold MDQ hold after rising edge of MEM_CLK tmem_clk*0.75-0.7 — ns A5.14 MEM_CLK Control Signals MDQ (Data) MA (Address) NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Active NOP WRITE NOP NOP NOP NOP NOP thold Row Column MBA (Bank Selects) datahold datavalid tvalid thold tvalid thold tvalid DQM (Data Mask) DMvalid DMhold |
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