MPC5200 datasheet(49/80 Pages) FREESCALE

49 / 80 page

Electrical and Thermal Characteristics

MPC5200 Data Sheet, Rev. 4

Freescale Semiconductor

Figure 34. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)

NOTE

Output timing was specified at a nominal 50 pF load.

Table 38. Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)

Sym

Description

Min

Max

Units

SpecID

Cycle time

1024

IP-Bus Cycle1

NOTES:

Inter Peripheral Clock is defined in the MPC5200 User Manual [1].

A11.21

Clock high or low time

512

IP-Bus Cycle1

A11.22

Slave select clock delay

15.0

—

A11.23

Output data valid

—

20.0

A11.24

Input Data setup time

20.0

—

A11.25

Input Data hold time

20.0

—

A11.26

Slave disable lag time

15.0

—

A11.27

Sequential Transfer delay

—

IP-Bus Cycle1

A11.28

Clock falling time

—

7.9

A11.29

Clock rising time

—

7.9

A11.30

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Input

MISO

Output

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