M28W640FCT_06 datasheet(7/77 Pages) STMICROELECTRONICS

7 / 77 page

M28W640FCT, M28W640FCB

Summary description

7/77

Summary description

The M28W640FCT and M28W640FCB are 64 Mbit (4 Mbit x 16) non-volatile Flash

memories that can be erased electrically at block level and programmed in-system on a

Word-by-Word basis using a 2.7V to 3.6V VDD supply for the circuitry and a 1.65V to 3.6V

VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to

speed up customer programming.

The devices feature an asymmetrical blocked architecture. They have an array of 135

blocks: 8 Parameter Blocks of 4 KWord and 127 Main Blocks of 32 KWord. The

M28W640FCT has the Parameter Blocks at the top of the memory address space while the

M28W640FCB locates the Parameter Blocks starting from the bottom. The memory maps

are shown in Figure 4: Block addresses.

The M28W640FCT and M28W640FCB feature an instant, individual block locking scheme

that allows any block to be locked or unlocked with no latency, enabling instant code and

data protection. All blocks have three levels of protection. They can be locked and locked-

down individually preventing any accidental programming or erasure. There is an additional

hardware protection against program and erase. When VPP ≤VPPLK all blocks are protected

against program or erase. All blocks are locked at Power Up.

Each block can be erased separately. Erase can be suspended in order to perform either

read or program in any other block and then resumed. Program can be suspended to read

data in any other block and then resumed. Each block can be programmed and erased over

100,000 cycles.

The device includes a 192 bit Protection Register to increase the protection of a system

design. The Protection Register is divided into a 64 bit segment and a 128 bit segment. The

64 bit segment contains a unique device number written by ST, while the second one is one-

time-programmable by the user. The user programmable segment can be permanently

protected. Figure 5, shows the Protection Register Memory Map.

Program and Erase commands are written to the Command Interface of the memory. An on-

chip Program/Erase Controller takes care of the timings necessary for program and erase

operations. The end of a program or erase operation can be detected and any error

conditions identified. The command set required to control the memory is consistent with

JEDEC standards.

The memory is offered in TSOP48 (12 × 20mm) and TFBGA48 (6.39 × 10.5mm, 0.75mm

pitch) packages and is supplied with all the bits erased (set to ’1’).

In order to meet environmental requirements, ST offers the M28W640FCT and

M28W640FCB in ECOPACK® packages. These packages have a Lead-free second level

interconnect. The category of second Level Interconnect is marked on the package and on

the inner box label, in compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

M28W640FCT 数据表(PDF) 7 Page - STMicroelectronics

M28W640FCT 数据表(HTML) 7 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

数据表下载