M28W640FCT_06 datasheet(15/77 Pages) STMICROELECTRONICS

15 / 77 page

M28W640FCT, M28W640FCB

Bus operations

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3.5

Automatic Standby

Automatic Standby provides a low power consumption state during Read mode. Following a

read operation, the device enters Automatic Standby after 150ns of bus inactivity even if

Chip Enable is Low, VIL, and the supply current is reduced to IDD1. The data Inputs/Outputs

will still output data if a bus Read operation is in progress.

3.6

Reset

During Reset mode when Output Enable is Low, VIL, the memory is deselected and the

outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power

consumption is reduced to the Standby level, independently from the Chip Enable, Output

Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this

operation is aborted and the memory content is no longer valid.

Table 2.

Bus operations(1)

X = VIL or VIH, VPPH = 12V ± 5%

Operation

VPP

DQ0-DQ15

Bus Read

VIL

VIH

Don't Care

Data Output

Bus Write

VIL

VIH

VIL

VIH

XVDD or VPPH

Data Input

Output Disable

VIL

VIH

Don't Care

Hi-Z

Standby

VIH

Don't Care

Hi-Z

Reset

VIL

Don't Care

Hi-Z

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