STE10A datasheet(9/82 Pages) STMICROELECTRONICS

9 / 82 page

STE10/100A

Pin description

9/82

C-BEB3

C-BEB2

C-BEB1

C-BEB0

I/O

Bus command and byte enable

IDSEL

Initialization device select. This signal is asserted when the

host issues configuration cycles to the STE10/100A.

FRAME#

I/O

Asserted by PCI bus master during bus tenure

IRDY#

I/O

Master device is ready to begin data transaction

TRDY#

I/O

Target device is ready to begin data transaction

DEVSEL#

I/O

Device select. Indicates that a PCI target device address has

been decoded

STOP#

I/O

PCI target device request to the PCI master to stop the

current transaction

PERR#

I/O

Data parity error detected, driven by the device receiving

data

SERR#

O/D

Address parity error

PAR

I/O

Parity. Even parity computed for AD[31:0] and C/BE[3:0];

master drives PAR for address and write data phase, target

drives PAR for read data phase.

Boot ROM/EEPROM interface

56~59

61~66

80~86

BrA0~3

BrA4~9

BrA10~15

BrA16/

LED M2 -

Fd/Col

I/O

ROM data bus

Provides up to 128Kbit EPROM or flash-ROM application

space.

This pin can be programmed as mode 2 LED display for full

duplex or collision status. It will be driven (LED on)

continually when a full duplex configuration is detected, or it

will be driven at a 20 Hz blinking frequency when a collision

status is detected in the half duplex configuration.

67~71

BrD0~4

BrD5/EDO

BrD6/EDI

BrD7/ECK

O/I

O/O

BootROM data bus (0~7)

EDO: Data output of serial EEPROM, data input to

STE10/100A

EDI: Data input to serial EEPROM, data output from

STE10/100A

ECK: Clock input to serial EEPROM, sourced by

STE10/100A

EECS

Chip select of serial EEPROM

BrCS#

BootROM chip select

BrOE#

BootROM read output enable for flash ROM application

BrWE#

BootROM write enable for flash ROM application.

Table 1.

Pin description (continued)

Pin no.

Name

Type

Description

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