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STE10A 数据表(PDF) 31 Page - STMicroelectronics |
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STE10A 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 82 page ![]() STE10/100A Registers and descriptors description 31/82 Table 5. STE10/100A configuration registers table offset b31 ----------- b16 b15 ---------- b0 00h Device ID* Vendor ID(1) 1. Automatically recalled from EEPROM when PCI reset is deserted DS(40h), bit15-8, is read/write able register SIG(80h) is hard wired register, read only 04h Status Command 08h Base class code Subclass ------ Revision # Step # 0ch ------ ------ Latency timer Cache line size 10h Base I/O address 14h Base memory address 18h~28h Reserved 2ch Subsystem ID(1) Subsystem vendor ID(1) 30h Boot ROM base address 34h Reserved Cap_Ptr 38h Reserved 3ch Max_Lat(1) Min-Gnt(1) Interrupt pin Interrupt line 40h Reserved Driver space Reserved 80h Signature of STE10/100A c0h PMC Next_Item_Ptr Cap_ID c4h Reserved PMCSR |
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