STE10A datasheet(49/82 Pages) STMICROELECTRONICS

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STE10/100A

Registers and descriptors description

49/82

9MPRE

Magic packet received enable. The STE10/100A

will include the “Magic Packet Received” event in

its set of wake-up events. If this bit is set,

STE10/100A will assert PMEST bit of PMR1

(CR49) after STE10/100A has received a Magic

packet.

Default 1 if PM

& WOL bits of

CSR 18 are

both enabled.

R/W

8LSCE

Link status changed enable. The STE10/100A

will include the “Link status changed” event in its

set of wake-up events. If this bit is set,

STE10/100A will assert PMEST bit of PMR1

after STE10/100A has detected a link status

changed event.

0R/W

7-3

---

Reserved

2WFR

Wake-up frame received,

1: Indicates STE10/100A has received a wake-

up frame. It is cleared by writing a 1 or upon

power-up reset. It is not affected by a hardware

or software reset.

XR/W1C*

1MPR

Magic packet received,

1: Indicates STE10/100A has received a magic

packet. It is cleared by writing a 1 or upon power-

up reset. It is not affected by a hardware or

software reset.

XR/W1C*

0LSC

Link status changed,

1: Indicates STE10/100A has detected a link

status change event. It is cleared by writing a 1

or upon power-up reset. It is not affected by a

hardware or software reset.

XR/W1C*

R/W1C*, Read only and write one cleared.

CSR14 (offset = 70h), WPDR – Wake-up pattern data register

Offset

16 15

0000h

Wake-up pattern 1 mask bits 31:0

0004h

Wake-up pattern 1 mask bits 63:32

0008h

Wake-up pattern 1 mask bits 95:64

000ch

Wake-up pattern 1 mask bits 127:96

0010h

CRC16 of pattern 1

Reserved

Wake-up

pattern 1

offset

0014h

Wake-up pattern 2 mask bits 31:0

0018h

Wake-up pattern 2 mask bits 63:32

001ch

Wake-up pattern 2 mask bits 95:64

0020h

Wake-up pattern 2 mask bits 127:96

Table 8.

Control/status register description (continued)

Bit #

Name

Description

Default

RW type

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