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UPD720100AGM-8EY 数据表(PDF) 16 Page - Renesas Technology Corp

部件名 UPD720100AGM-8EY
功能描述  MOS INTEGRATED CIRCUIT
PDF  34 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD720100AGM-8EY 数据表(HTML) 16 Page - Renesas Technology Corp

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Data Sheet S15535EJ3V0DS
14
µPD720100A
USB Interface Block
Parameter
Symbol
Conditions
MIN
MAX
Unit
Serial Resistor between DP (DM) and
RSDP (RSDM).
RS
35.64
36.36
Output pin impedance
ZHSDRV
Includes RS resistor
40.5
49.5
Input Levels for Low-/full-speed:
High-level input voltage (drive)
VIH
2.0
V
High-level input voltage (floating)
VIHZ
2.7
3.6
Low-level input voltage
VIL
0.8
V
Differential input sensitivity
VDI
(D+) − (D−)
0.2
V
Differential Common mode Range
VCM
Includes VDI range
0.8
2.5
V
Output Levels for Low-/full-speed:
High-level output voltage
VOH
RL of 14.25 k
Ω to GND
2.8
3.6
V
Low-level output voltage
VOL
RL of 1.425 k
Ω to 3.6 V
0.0
0.3
V
SE1
VOSE1
0.8
V
Output signal crossover point voltage
VCRS
1.3
2.0
V
Input Levels for High-speed:
High-speed squelch detection threshold
(differential signal)
VHSSQ
100
150
mV
High-speed disconnect detection
threshold (differential signal)
VHSDSC
525
625
mV
High-speed data signaling common
mode voltage range
VHSCM
−50
+500
mV
High-speed differential input signaling
level
See Figure 2-4.
Output Levels for High-speed:
High-speed idle state
VHSOI
−10.0
+10
mV
High-speed data signaling high
VHSOH
360
440
mV
High-speed data signaling low
VHSOL
−10.0
+10
mV
Chirp J level (different signal)
VCHIRPJ
700
1100
mV
Chirp K level (different signal)
VCHIRPK
−900
−500
mV



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