UPD720100AGM-8EY datasheet(21/34 Pages) RENESAS

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Data Sheet S15535EJ3V0DS

µPD720100A

AC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to

+70°C)

PCI Interface Block

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

PCI clock cycle time

tcyc

PCI clock pulse, high-level width

thigh

PCI clock pulse, low-level width

tlow

PCI clock, rise slew rate

Scr

0.2 VDD to 0.6 VDD

V/ns

PCI clock, fall slew rate

Scf

0.2 VDD to 0.6 VDD

V/ns

PCI reset active time

(vs. power supply stability)

trst

PCI reset active time (vs. CLK Start)

trst-clk

100

µs

Output float delay time (vs. RST0

↓)

trst-off

PCI reset rise slew rate

Srr

mV/ns

PCI bus signal output time (vs. PCLK

↑)

tval

PCI point-to-point signal output time

(vs. PCLK

↑)

tval (ptp)

REQ0

Output delay time (vs. PCLK

↑)

ton

Output float delay time (vs. PCLK

↑)

toff

Input setup time (vs. PCLK

↑)

tsu

Point-to-point input setup time (vs. PCLK

↑)

tsu (ptp)

GNT0

Input hold time

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