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UPD720100AGM-8EY 数据表(PDF) 22 Page - Renesas Technology Corp

部件名 UPD720100AGM-8EY
功能描述  MOS INTEGRATED CIRCUIT
PDF  34 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD720100AGM-8EY 数据表(HTML) 22 Page - Renesas Technology Corp

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Data Sheet S15535EJ3V0DS
20
µPD720100A
USB Interface Block
(1/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Low Source Electrical Characteristics
Rise time (10% - 90%)
tLR
CL = 200 pF – 600 pF,
RS = 36
Ω
75
300
ns
Fall time (90% - 10%)
tLF
CL = 200 pF – 600 pF,
RS = 36
Ω
75
300
ns
Differential Rise and Fall Time matching
tLRFM
(tLR/tLF)
80
125
%
Low-speed Data Rate
tLDRATHS
Average bit rate
1.49925
1.50075
Mbps
Source Jitter Total (including frequency
tolerance):
To Next Transition
For Paired Transitions
tDDJ1
tDDJ2
−25
−14
+25
+14
ns
ns
Source Jitter for Differential Transition to
SE0 transition
tLDEOP
-40
+100
ns
Receiver Jitter:
To Next Transition
For Paired Transitions
tUJR1
tUJR2
−152
−200
+152
+200
ns
ns
Source SE0 interval of EOP
tLEOPT
1.25
1.50
µs
Receiver SE0 interval of EOP
tLEOPR
670
ns
Width of SE0 interval during differential
transition
tFST
210
ns
Full-speed Source Electrical Characteristics
Rise time (10% - 90%)
tFR
CL = 50 pF,
RS = 36
Ω
4
20
ns
Fall time (90% - 10%)
tFF
CL = 50 pF,
RS = 36
Ω
4
20
ns
Differential Rise and Fall Time matching
tFRFM
(tFR/tFF)
90
111.11
%
Full-speed Data Rate
tFDRATHS
Average bit rate
11.9940
12.0060
Mbps
Frame Interval
tFRAME
0.9995
1.0005
ms
Consecutive Frame Interval Jitter
tRFI
No clock adjustment
42
ns
Source Jitter Total (including frequency
tolerance):
To Next Transition
For Paired Transitions
tDJ1
tDJ2
−3.5
−4.0
+3.5
+4.0
ns
ns
Source Jitter for Differential Transition to
SE0 transition
tFDEOP
−2
+5
ns
Receiver Jitter:
To Next Transition
For Paired Transitions
tJR1
tJR2
−18.5
−9
+18.5
+9
ns
ns
Source SE0 interval of EOP
tFEOPT
160
175
ns
Receiver SE0 interval of EOP
tFEOPR
82
ns
Width of SE0 interval during differential
transition
tFST
14
ns



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