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UPD720100AGM-8EY 数据表(PDF) 23 Page - Renesas Technology Corp

部件名 UPD720100AGM-8EY
功能描述  MOS INTEGRATED CIRCUIT
PDF  34 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

UPD720100AGM-8EY 数据表(HTML) 23 Page - Renesas Technology Corp

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Data Sheet S15535EJ3V0DS
21
µPD720100A
(2/2)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
High-speed Source Electrical Characteristics
Rise time (10% - 90%)
tHSR
500
ps
Fall time (90% - 10%)
tHSF
500
ps
Driver waveform
See Figure 2-6.
High-speed Data Rate
tHSDRAT
479.760
480.240
Mbps
Microframe Interval
tHSFRAM
124.9375
125.0625
µs
Consecutive Microframe Interval Difference
tHSRFI
4
high-speed
Bit
times
Data source jitter
See Figure 2-6.
Receiver jitter tolerance
See Figure 2-4.
Hub event Timings
Time to detect a downstream facing port
connect event
tDCNN
2.5
2000
µs
Time to detect a disconnect event at a
downstream facing port:
tDDIS
2.0
2.5
µs
Duration of driving resume to a
downstream port
tDRSMDN
Nominal
20
ms
Time from detecting downstream resume to
rebroadcast.
tURSM
1.0
ms
Inter-packet Delay for packets traveling in
same direction for high-speed
tHSIPDSD
88
Bit
times
Inter-packet Delay for packets traveling in
opposite direction for high-speed
tHSIPDOD
8
Bit
times
Inter-packet delay for root hub response for
high-speed
tHSRSPIPD1
192
Bit
times
Time for which a Chirp J or Chirp K must
be continuously detected during Reset
handshake
tFILT
2.5
µs
Time after end of device Chirp K by which
hub must start driving first Chirp K
tWTDCH
100
µs
Time for which each individual
Chirp J or Chirp K in the chirp sequence is
driven downstream during reset
tDCHBIT
40
60
µs
Time before end of reset by which a hub
must end its downstream chirp sequence
tDCHSE0
100
500
µs



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