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数据搜索系统，热门电子元器件搜索 |
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ST7LITE0X 数据表(PDF) 58 Page - STMicroelectronics |
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ST7LITE0X 数据表(HTML) 58 Page - STMicroelectronics |
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58 / 125 page  ST7LITE0x, ST7LITESx 58/125 12-BIT AUTORELOAD TIMER (Cont’d) AUTO RELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h) AUTO RELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by soft- ware. The ATR register value is automatically loaded into the upcounter when an overflow oc- curs. The register value is used to set the PWM frequency. PWM0 DUTY CYCLE REGISTER HIGH (DCR0H) Read / Write Reset Value: 0000 0000 (00h) PWM0 DUTY CYCLE REGISTER LOW (DCR0L) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. The high register must be written first. In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWM0 output signal (see Figure 34). In Output Compare mode, (OE0=0 in the PWMCR register) they define the value to be compared with the 12- bit upcounter value. PWM0 CONTROL/STATUS REGISTER (PWM0CSR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:2= Reserved, must be kept cleared. Bit 1 = OP0 PWM0 Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal. 0: The PWM0 signal is not inverted. 1: The PWM0 signal is inverted. Bit 0 = CMPF0 PWM0 Compare Flag. This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 regis- ter value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 70 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 15 8 0 0 0 0 DCR11 DCR10 DCR9 DCR8 70 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0 70 0 000 00 OP0 CMPF0 1 |
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