ST7LITE0X datasheet(25/125 Pages) STMICROELECTRONICS

25 / 125 page

ST7LITE0x, ST7LITESx

25/125

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a range of utility features for

securing the application in critical situations (for

example in case of a power brown-out), and re-

ducing the number of external components.

Main features

■ Clock Management

– 1 MHz internal RC oscillator (enabled by op-

tion byte)

– External Clock Input (enabled by option byte)

– PLL for multiplying the frequency by 4 or 8

(enabled by option byte)

■ Reset Sequence Manager (RSM)

■ System Integrity Management (SI)

– Main supply Low voltage detection (LVD) with

reset generation (enabled by option byte)

– Auxiliary Voltage detector (AVD) with interrupt

capability for monitoring the main supply (en-

abled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The ST7 contains an internal RC oscillator with an

accuracy of 1% for a given device, temperature

and voltage. It must be calibrated to obtain the fre-

quency required in the application. This is done by

software writing a calibration value in the RCCR

(RC Control Register).

Whenever the microcontroller is reset, the RCCR

returns to its default value (FFh), i.e. each time the

device is reset, the calibration value must be load-

ed in the RCCR. Predefined calibration values are

stored in EEPROM for 3.0 and 5V VDD supply volt-

ages at 25°C, as shown in the following table.

Notes:

– See “ELECTRICAL CHARACTERISTICS” on

page 82. for more information on the frequency

and accuracy of the RC oscillator.

– To improve clock stability and frequency accura-

cy, it is recommended to place a decoupling ca-

pacitor, typically 100nF, between the VDD and

VSS pins as close as possible to the ST7 device.

– These two bytes are systematically programmed

by ST, including on FASTROM devices. Conse-

quently, customers intending to us e FASTROM

service must not use these two bytes.

– RCCR0 and RCCR1 calibration values will be

erased if the read-out protection bit is reset after

it has been set. See “Read out Protection” on

page 15.

Caution: If the voltage or temperature conditions

change in the application, the frequency may need

to be recalibrated.

Refer to application note AN1324 for information

on how to calibrate the RC frequency using an ex-

ternal reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequen-

cy from the RC oscillator or the external clock by 4

or 8 to obtain fOSC of 4 or 8 MHz. The PLL is ena-

bled and the multiplication factor of 4 or 8 is select-

ed by 2 option bits.

– The x4 PLL is intended for operation with VDD in

the 2.4V to 3.3V range

– The x8 PLL is intended for operation with VDD in

the 3.3V to 5.5V range

Refer to Section 15.1 for the option byte descrip-

tion.

If the PLL is disabled and the RC oscillator is ena-

bled, then fOSC = 1MHz.

If both the RC oscillator and the PLL are disabled,

fOSC is driven by the external clock.

RCCR

Conditions

ST7FLITE09

Address

ST7FLITE05/

ST7FLITES5

Address

RCCR0

VDD=5V

TA=25°C

fRC=1MHz

1000h and

FFDEh

RCCR1

VDD=3.0V

TA=25°C

fRC=700KHz

1001h and-

FFDFh

ST7LITE0X 数据表(PDF) 25 Page - STMicroelectronics

ST7LITE0X 数据表(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载