ST7LITE0X datasheet(92/125 Pages) STMICROELECTRONICS

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13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA.

13.5.1 General Timings

13.5.2 External Clock Source

Notes:

1. Guaranteed by Design. Not tested in production.

2. Data based on typical application software.

3. Time measured between interrupt event and interrupt vector fetch.

∆t

c(INST) is the number of tCPU cycles needed to fin-

ish the current instruction execution.

4. Data based on design simulation and/or technology characteristics, not tested in production.

Figure 60. Typical Application with an External Clock Source

Symbol

Parameter 1)

Conditions

Min

Typ 2)

Max

Unit

tc(INST)

Instruction cycle time

fCPU=8MHz

tCPU

250

375

1500

tv(IT)

Interrupt reaction time 3)

tv(IT) = ∆tc(INST) + 10

fCPU=8MHz

tCPU

1.25

2.75

µs

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VCLKINH

CLKIN input pin high level voltage

see Figure 60

0.7xVDD

VDD

VCLKINL

CLKIN input pin low level voltage

VSS

0.3xVDD

tw(CLKINH)

tw(CLKINL)

CLKIN high or low time 4)

tr(CLKIN)

tf(CLKIN)

CLKIN rise or fall time 4)

CLKIN Input leakage current

VSS≤VIN≤VDD

±1

µA

CLKIN

fOSC

EXTERNAL

ST72XXX

CLOCK SOURCE

VCLKINL

VCLKINH

tr(CLKIN)

tfCLKIN)

tw(CLKINH)

tw(CLKINL)

90%

10%

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