Custom Silicon Solutions, Inc. ©2009

4

Version 1.1, May 2009

CSS555C

Micropower Timer (with Internal Timing Capacitor)

Electrical Characteristics (cont)

Temperature = -40°C to +85°C, Test Circuit #1, unle ss otherwise specified

(If VDD < 1.8V, “Low Voltage” mode must be selected to provide adequate comparator input levels. EE Bit5 = 1)

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Supply Range

VDD

Standard VDD (EE Bit 5 = 0)

Low VDD (EE Bit 5 = 1)

1.8

1.2

5.5

5.5

V

V

Supply Current

(No DC load on OUTPUT pin, RL = ∞)

IDD

VDD = 1.5V

VDD = 3.0V

VDD = 5.0V

2.2

3.1

4.3

5.0

7.5

10.0

µA

µA

µA

Timing Accuracy

(Micro power setting, EE Bit 4 = 0)

(Monostable & Astable Modes)

TAVDD

RA(B) = 1M , CT = 0.001

µF

VDD = 1.5V

VDD = 3.0V

VDD = 5.0V

1.0

1.0

1.0

2.5

2.5

2.5

%

%

%

Timing Drift with Temperature

(Monostable & Astable Modes)

TDTEMP

RA(B) = 1M , CT = 0.001

µF

VDD = 1.5V

VDD = 3.0V

VDD = 5.0V

45

35

35

ppm/°C

ppm/°C

ppm/°C

Timing Shift with Supply Voltage

(Monostable & Astable Modes)

TSVDD

RA(B) = 1M , CT = 0.001

µF

VDD = 1.5V

VDD = 3.0V

VDD = 5.0V

0.10

0.15

0.15

%/V

%/V

%/V

Maximum Oscillator Frequency

fMAX

RA,B = 4.7K , CTI = 100 pF

1

MHz

Control Voltage

VCTRL

Standard VDD (EE Bit 5 = 0)

Low VDD (EE Bit 5 = 1)

64

88

67

90

70

92

% V

% V

Trigger Voltage

VTRIG

Standard VDD (EE Bit 5 = 0)

Low VDD (EE Bit 5 = 1)

30

8

33

10

36

12

% V

% V

Reset Voltage

VRST

0.3 x VDD

0.5 x VDD

0.7 x VDD

V

Output Voltage

(Timer Output Pin)

VOL

VDD = 1.5V, ISINK = 1 mA

VDD = 3.0V, ISINK = 4 mA

VDD = 5.0V, ISINK = 10 mA

0.07

0.16

0.31

0.20

0.30

0.60

V

V

V

VOH

VDD = 1.5V, ISOURCE = 1 mA

VDD = 3.0V, ISOURCE = 4 mA

VDD = 5.0V, ISOURCE = 10 mA

1.30

2.70

4.40

1.40

2.85

4.73

V

V

V

Discharge Saturation Voltage

(Discharge Output Pin)

VDIS

VDD = 1.5V, ISINK = 2.5 mA

VDD = 3.0V, ISINK = 10 mA

VDD = 5.0V, ISINK = 25 mA

0.07

0.18

0.36

0.20

0.30

0.60

V

V

V

Input Current

(Trigger, Reset & Threshold Inputs)

IIN

VDD = 5.5V

VIN = 0.0V to 5.5V

10

pA

Discharge Leakage Current

IDIS

VDD = 5.5V

1

100

nA

Output Rise & Fall Times

tR, tF

VDD = 3.0V, CL = 10 pF

5

ns

Input Capacitance

CIN

10

pF

Internal Timing Capacitor (NP0)

CTI

Trim Resolution = 0.2pF

99

100

101

pF

Table 3

Test Circuit #1

Figure 5

VDD

RA

Trigger

Output

Reset

CT

VDD

Dischg

Thresh

Control

CSS555C

VSS

Trigger

Output

Reset

RB

Note:

CT ≡ External Timing Capacitor

CTI ≡ Internal Timing Capacitor

CTOTAL ≡ CT + CTI