CSS555C datasheet(7/13 Pages) ETC

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Version 1.1, May 2009

CSS555C

Micropower Timer (with Internal Timing Capacitor)

Astable Operation

(Standard 555 Mode)

The circuit in Figure 12 shows the astable or “free running

oscillator” configuration. If the counter setting equals one,

the counter is bypassed and the device operates like a

standard 555 timer.

With the TRIGGER input tied to

THRESHOLD, a new timing cycle is started each time VTH

drops below the lower comparator trip level.

Figure 12 – Astable Circuit (Std. Mode)

The capacitor charges to ⅔ VDD through (RA+RB) and

discharges to ⅓ VDD through RB. (As in the monostable

mode, the trip levels are changed to 10% & 90% for low

supply voltages. This selection is made via the EEPROM.)

The duty cycle is determined by the ratio of RA and RB.

Typical signal waveforms are shown in Figure 13. The

RESET input must be held high for the oscillator to be

active.

If RESET is brought low, the OUTPUT pin is

immediately forced low and oscillation halts. Equations for

the free running oscillator are provided in the following

paragraph.

Figure 13 – Astable Waveforms (Std. Mode)

Note: The TRIGGER signal is connected to VTH

Free Running Oscillator Equations:

For standard supply voltages (VLOW Bit = 0)

Oscillator Period (tOSC) = 0.695 x (RA+2RB) x CTotal

Osc. Freq. (fOSC) = 1/tOSC = 1.44/[(RA+2RB) x CTotal]

where

CTotal = CT + CTI

CT = External timing capacitor

CTI = Internal 100pF timing capacitor

For low voltage mode (VLOW Bit = 1)

Oscillator Period (tOSC) = 2.197 x (RA+2RB) x CTotal

Osc. Freq. (fOSC) = 1/tOSC = 0.455/[(RA+2RB) x CTotal]

Duty Cycle = RB/(RA+2RB)

The

chart in

Figure

shows

nominal oscillator

frequencies for resistor values (RA+2RB) from 1K to 10M

and capacitor values from 100pF to 1uF. The resulting

frequency range extends from 1 Hz to 1 MHz. (For this

chart, the counter is bypassed; Mult = 1.)

0.0001

0.0010

0.0100

0.1000

1.0000

100

1000

10000

100000

1000000

Frequency (Hz)

Figure 14 – Astable Frequency Chart (Std. Mode)

Astable Operation

(Extended Period or “EP” Mode)

The circuit in Figure 15 employs the internal decade

counter to divide the 555 oscillator frequency by the

multiplier setting.

The multiplier value, 10 to 10

6, is

selected by the EEPROM.

The 555 analog block is

configured as a free running oscillator, which supplies the

input clock to the counter.

The oscillator runs when

RESET is high (logic one) and TRIGGER is low. Each

divide by 10 stage of the decade counter consists of a

divide by 5 followed by a divide by 2. This configuration

provides a 50% output duty cycle no matter which multiplier

setting is selected. Waveforms for this mode are shown in

Figure 16.

RA+2RB =

10M

100K

10K

Green:

Low VDD

Blue:

Std. VDD

OUTPUT

VCAP

⅔ VDD

⅓ VDD

RESET

Mult = 1

VDD

Output

Reset

VDD

Dischg

Thresh

Control

CSS555C

VSS

Trigger

Output

Reset

Output

Reset

Optional

VTH

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