Custom Silicon Solutions, Inc. ©2009

8

Version 1.1, May 2009

CSS555C

Micropower Timer (with Internal Timing Capacitor)

Figure 15 – Astable Circuit (EP Mode)

Figure 16 – Astable Waveforms (EP Mode)

Free Running Oscillator Equations:

For standard supply voltages (VLOW Bit = 0)

Oscillator Period (tOSC) = 0.695 x (RA+2RB) x CTotal

Osc. Freq. (fOSC) = 1/tOSC = 1.44/[(RA+2RB) x CTotal]

Output Frequency = fOSC/Mult

where

CTotal = CT + CTI

CT = External timing capacitor

CTI = Internal 100pF timing capacitor

For low voltage mode (VLOW Bit = 1)

Oscillator Period (tOSC) = 2.197 x (RA+2RB) x CTotal

Osc. Freq. (fOSC) = 1/tOSC = 0.455/[(RA+2RB) x CTotal]

Output Frequency = fOSC/Mult

Duty Cycle = 50%

The

chart in

Figure

17

shows

nominal oscillator

frequencies for multiplier settings from 1 to 10

6 and resistor

values (RA+2RB) from 1K

to 10M . (The internal timing

capacitor, CTI, equals 100pF.

No external timing

capacitor.) The resulting frequencies range from less than

1Hz to 1MHz.

1

10

100

1000

10000

100000

1000000

1

10

100

1000

10000

100000

1000000

Frequency (Hz)

Figure 17 – Astable Frequency Chart (EP Mode)

EEPROM (Configuration Memory)

An internal EEPROM provides two bytes of nonvolatile

memory that stores the configuration information and the

100pF capacitor trim setting. The configuration bits control

the multiplier setting (1 to 10

6), the power setting (micro or

low) and the comparator trip levels (standard or low

voltage).

(See Tables 1A & 1B for more details.)

By

employing an internal EEPROM for configuration control,

the pin count and pin functions remain compatible with

existing 555 IC’s.

The EEPROM includes a high voltage generator.

No

special signal levels are required to Read or Write to it.

Access to the EEPROM is enabled by forcing the

CONTROL pin to GND. (This pin is normally left open and

an internal voltage divider holds it at ⅔VDD.)

With

CONTROL held at GND, the TRIGGER and RESET pins

are redefined to be SCLK (Serial Clock) and SDIN (Serial

Data In).

Data from the EEPROM can be read at the

OUTPUT pin. The interface is simple and straightforward.

It can support programming individual units or devices

installed in their application circuit. A detailed description

of the serial interface is provided in Application Note

AN555-1 (“CSS555C EEPROM Serial Interface”).

A

development

kit

is

available

and

provides

both

programming and evaluation capabilities.

It uses a

standard PC and one USB port. Please contact Custom

Silicon Solutions for more information.

The core EEPROM cell is a differential, floating gate circuit.

Like an SRAM, it features zero static current. Its output

data is valid whenever the supply voltage is above 1.0V. It

has excellent data retention and endurance characteristics.

Data retention is greater than 10 years at 85°C and its

endurance (maximum number of Store cycles) is greater

than 100,000 cycles. A typical Store operation can be

performed in less than 25 msec.

TRIGGER

OUTPUT

VCAP

0V

⅔ VDD

⅓ VDD

RESET

Mult = 10

RA+2RB =

10M

1M

100K

10K

1K

CT = 100pF

Green:

Low VDD

Blue:

Std. VDD

VDD

RA

Trigger

Output

Reset

CT

VDD

Dischg

Thresh

Control

CSS555C

VSS

Trigger

Output

Reset

Trigger

Output

Reset

RB

VTH

Optional