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STMPE811 数据表(PDF) 10 Page - STMicroelectronics |
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STMPE811 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 66 page ![]() I2C interface STMPE811 10/66 Doc ID 14489 Rev 5 4 I2C interface The addressing scheme of STMPE811 is designed to allow up to 2 devices to be connected to the same I2C bus. Figure 4. STMPE811 I2C interface For the bus master to communicate to the slave device, the bus master must initiate a Start condition and be followed by the slave device address. Accompanying the slave device address, is a read/write bit (R/W). The bit is set to 1 for read and 0 for write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledge on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction. Figure 5. I2C timing diagram Table 6. I2C address ADDR0 Address 00 x 82 10 x 88 ADDR0 SCLK SDAT SCLK SDAT GND VCC STMPE811 AI00589 SDA P tSU:STO tSU:STA tHD:STA SR SCL tSU:DAT tF tHD:DAT tR tHIGH tLOW tHD:STA tBUF S P |
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