WM8196

Production Data

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PD Rev 4.3 March 2007

6

ELECTRICAL CHARACTERISTICS

Test Conditions

°C, MCLK = 24MHz unless otherwise stated.

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)

Conversion Rate

12

MSPS

Full-scale input voltage range

(see Note 1)

0.4

4.08

Vp-p

Vp-p

Input signal limits (see Note 2)

0

AVDD

V

Full-scale transition error

Gain = 0dB;

PGA[7:0] = 4B(hex)

20

mV

Zero-scale transition error

Gain = 0dB;

PGA[7:0] = 4B(hex)

20

mV

Differential non-linearity

DNL

1.25

LSB

Integral non-linearity

INL

25

LSB

Channel to channel gain matching

1

%

Total output noise

Min Gain

Max Gain

4.5

14

LSB rms

LSB rms

References

Upper reference voltage

VRT

2.85

V

Lower reference voltage

VRB

1.35

V

Input return bias voltage

VRX

1.4

1.65

1.6

V

Diff. reference voltage (VRT-VRB)

1.5

V

Output resistance VRT, VRB, VRX

1

Ω

VRLC/Reset-Level Clamp (RLC)

RLC switching impedance

50

Ω

VRLC short-circuit current

2

mA

VRLC output resistance

2

Ω

VRLC Hi-Z leakage current

VRLC = 0 to AVDD

1

µA

RLCDAC resolution

4

bits

RLCDAC step size, RLCDAC = 0

AVDD=5V

0.25

V/step

RLCDAC step size, RLCDAC = 1

0.17

V/step

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 0

AVDD=5V

0.39

V

RLCDAC output voltage at

code 0(hex), RLCDACRNG = 1

0.26

V

RLCDAC output voltage at

code F(hex) RLCDACRNG, = 0

AVDD=5V

4.16

V

RLCDAC output voltage at

code F(hex), RLCDACRNG = 1

2.81

V

VRLC deviation

-50

+50

mV

Offset DAC, Monotonicity Guaranteed

Resolution

8

bits

Differential non-linearity

DNL

0.1

0.5

LSB

Integral non-linearity

INL

0.25

1

LSB

Step size

2.04

mV/step

Output voltage

Code 00(hex)

Code FF(hex)

-260

+260

mV

mV

Notes:

1.

Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.

2.

Input signal limits are the limits within which the full-scale input voltage signal must lie.