WM8196

Production Data

w

PD Rev 4.3 March 2007

19

SCK

SEN

SDI

a5

1

a3 a2 a1 a0

x

x

xxx

xxx

Address

Data Word

d7 d6 d5 d4 d3 d2 d1 d0

Output Data Word

SDO/

OP[7]

OEB

Figure 18 Serial Interface Register Read-back

TIMING REQUIREMENTS

To use this device a master clock (MCLK) of up to 24MHz and a per-pixel synchronisation clock

(VSMP) of up to 12MHz are required. These clocks drive a timing control block, which produces

internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum

sample rates for the various modes are shown in Table 5.

PROGRAMMABLE VSMP DETECT CIRCUIT

The VSMP input is used to determine the sampling point and frequency of the WM8196. Under

normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling

frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on

the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal

may not be readily available. The programmable VSMP detect circuit in the WM8196 allows the

sampling point to be derived from any signal of the correct frequency, such as a CCD shift register

clock, when applied to the VSMP pin.

When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge

(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.

This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.

Figure 19 shows the internal VSMP pulses that can be generated by this circuit for a typical clock

input signal. The internal VSMP pulse is then applied to the timing control block in place of the

normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising

MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.