WM8196

Production Data

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PD Rev 4.3 March 2007

13

DEVICE DESCRIPTION

INTRODUCTION

A block diagram of the device showing the signal path is presented on Page 1.

The WM8196 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then

processes the sampled video signal with respect to the video reset level or an internally/externally

generated reference level using either one or three processing channels.

Each processing channel consists of an Input Sampling block with optional Reset Level Clamping

(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit

Programmable Gain Amplifier (PGA).

The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from

the ADC is presented on an 8-bit wide bi-directional bus, with optional 8 or 4-bit multiplexed formats.

On-chip control registers determine the configuration of the device, including the offsets and gains

applied to each channel. These registers are programmable via a serial interface.

INPUT SAMPLING

The WM8196 can sample and process one to three inputs through one or three processing channels

as follows:

Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for

each pixel and a separate channel processes each input. The signals are then multiplexed into the

ADC, which converts all three inputs within the pixel period.

Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the

corresponding channel, and converted by the ADC. The choice of input and channel can be changed

via the control interface, e.g. on a line-by-line basis if required.

Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into

the red channel for processing before being converted by the ADC. The input selected can be

switched in turn (RINP

→ GINP → BINP → RINP…) together with the PGA and Offset DAC control

registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling

sequences can be generated via the control registers. This mode causes the blue and green

channels to be powered down. Refer to the Line-by-Line Operation section for more details.

RESET LEVEL CLAMPING (RLC)

To ensure that the signal applied to the WM8196 lies within its input range (0V to AVDD) the CCD

WM8196 side of this capacitor to a suitable voltage during the CCD reset period.

A typical input configuration is shown in Figure 9. An internal clamp pulse, CL, is generated from

MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8196 side of

RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to

the CDS/non-CDS Processing section.