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WM8720EDS/R 数据表(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8720EDS/R 数据表(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 17 page ![]() WM8720 Production Data w PD Rev 4.0. February 2005 9 AUDIO DATA INTERFACE The Serial Data interface to WM8720 is fully compatible with both normal (MSB first, right-justified) or I 2S interfaces. Data may be ‘packed’ (number of serial bit clocks per LRCIN period is exactly 2 times the number of data bits, i.e. normally 32 in 16-bit mode) or unpacked (more than 32 bit clocks per LRCIN period). The WM8720 will automatically detect 16-bit packed data being sent to the device in normal mode, and accept the data in this input format accordingly. I 2S MODE DESCRIPTION 0 Normal format (MSB-first, right justified) 1 I 2S format (Philips serial data protocol ) Table 2 Serial Interface Formats MSB MSB LSB LSB LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN 1/fs 12 3 n n-1 n-2 12 3 n n-1 n-2 Figure 4 Normal Data Input Timing MSB MSB LSB LSB LEFT CHANNEL RIGHT CHANNEL LRCIN BCKIN DIN 1/fs 123 n n-1 n-2 12 3 n n-1 n-2 Figure 5 I 2S Data Input Timing |
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