WM8720

Production Data

w

PD Rev 4.0. February 2005

13

AX[7:0]

ATTENUATION LEVEL

00(hex)

-

∞dB (mute)

01(hex)

-48.16dB

:

:

:

:

:

:

Fe(hex)

-0.07dB

FF(hex)

0dB

Table 9 Attenuation Control Levels

Bit 8 in register 0 (LDL) is used to control the loading of attenuation data in AL[7:0]. When LDL is set

to 0, attenuation data will be loaded into AL[7:0], but it will not affect the attenuation level until LDL is

set to 1. LDR in register 1 has the same function for right channel attenuation.

Register 1 (A[1:0] = 01) is used to control right channel attenuation in a similar manner.

Bit 2 in register 3 (A1[1:0] = 11) is used to control the attenuator (ATC). When ATC is high, the

attenuation data loaded in program register 0 is used for both the left and the right channels. When

ATC is low, the attenuation data for each register is applied separately to left and right channels.

LEFT AND RIGHT DACS SOFT MUTE CONTROL

Soft mute is controlled by setting bit MU, register 2:bit 0. A high level on MU (MU = 1) will cause the

output to be muted, the effect of which is to ramp the signal down in the digital domain so that there

is no discernible click. This can be seen in Figure 6 Mute Circuit Operation.

DE-EMPHASIS CONTROL

Bit 1 (DE) in register 2 is used to control digital de-emphasis. A low level on bit 1 (DE = 0) disables

de-emphasis whilst a high level enables de-emphasis (DE = 1). De-emphasis applied to the filters

shapes the frequency response of the digital filter according to the input sample frequency.

LEFT AND RIGHT DACS OPERATION CONTROL

Bit 2 (OPE) in register 2 is used for operation control. With OPE = 0 (default) the device functions

normally. With OPE = 1 the device is disabled and the outputs are held at midrail. Current

consumption of the digital section is minimized, but analogue sections remain active in order to

preserve DC levels.

INPUT AUDIO WORD RESOLUTION

WM8720 allows maximum flexibility over the control of the audio data interface, allowing selection of

format type, word length, and sample rates. Bits 3 and 4 of register 2 (IW[1:0]) are used to determine

the input word resolution. WM8720 supports 16-bit, 18-bit, 20-bit and 24-bit formats as described in

Table 10.

BIT 4 (IW1)

BIT 3 (IW0)

INPUT RESOLUTION

0

0

16-bit data word

0

1

20-bit data word

1

0

24-bit data word

1

1

18-bit data word

Table 10 Input Data Resolution